Semiconductor device and method of manufacturing the same

ABSTRACT

There are contained first and second conductive plugs formed in first insulating layer, an island-like oxygen-barrier metal layer for covering the first conductive plug, an oxidation-preventing insulating layer formed on the first insulating layer to cover side surfaces of the oxygen-barrier metal layer, a capacitor having a lower electrode formed on the oxygen-barrier metal layer and the oxidation-preventing insulating layer, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, a second insulating layer for covering the capacitor and the oxidation-preventing insulating layer, a third hole formed in respective layers from the second insulating layer to the oxidation-preventing insulating layer on the second conductive plug, and a third conductive plug formed in the third hole and connected to the second conductive plug.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 10/388,596,filed Mar. 17, 2003, which is based on and claims priority to JapanesePatent Applications No. 2002-74566, filed on Mar. 18, 2002, No.2002-249448, filed on Aug. 28, 2002, and No. 2003-64601, filed on Mar.11, 2003, the contents of which are fully incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method ofmanufacturing the same and, more particularly, a semiconductor devicehaving a capacitor and a method of manufacturing the same.

2. Description of the Prior Art

The ferroelectric capacitor of FeRAM (Ferroelectric Random AccessMemory) that is mass-produced currently has the planar structure.

However, the capacitor having the stacked structure, a cell area ofwhich can be reduced smaller, is needed in future in reply to therequest for the higher integration. The stacked structure has theconductive plug, which is used to provide contact with the semiconductorsubstrate, directly under the lower electrode of the ferroelectriccapacitor. As set forth in Patent Application Publication (KOKAI)2001-443476, for example, it is normal that tungsten or polysilicon isused as the material of such conductive plug.

While, the FeRAM and the logic device are hybrid-integrated in manyproducts. For example, there are the semiconductor chip used in thesecurity field that needs the authentication, the IC card that isutilized gradually in the local self-governing body, etc.

In the logic semiconductor device, it is common that the process usingthe tungsten plug is employed to connect the underlying conductivepattern and the overlying conductive pattern. It is of course that, asthe spice parameter used to design the circuit, the resistance value ofthe tungsten plug is employed.

Therefore, if the significances to make efficient use of accumulatedcircuit design properties and to lower the development man-hour/cost areconsidered, it has the great merit to use the tungsten plug as thecontact plug in the logic hybrid-integrated FeRAM like the prior art.

Next, steps of forming the memory cell having the stacked capacitor willbe explained hereunder.

First, steps required until a structure shown in FIG. 1A is formed willbe explained hereunder.

An element isolation insulating film 102 is formed around an elementforming region of a silicon substrate 101, and then a well 103 is formedin the element forming region. Then, two MOS transistors 104 are formedin one well 103.

The MOS transistors 104 have gate electrodes 104 b formed on the well103 via a gate insulating film 104 a, and impurity diffusion regions 104c, 104 d formed in the well 103 on both sides of the gate electrodes 104b to serve as the source/drain. Also, insulating sidewalls 105 used toform high concentration impurity regions 104 e in the impurity diffusionregions 104 c, 104 d are formed on both side surfaces of the gateelectrodes 104 b.

Then, a transistor protection insulating film 106 for covering the MOStransistors 104 is formed on the silicon substrate 101, and then a firstinterlayer insulating film 107 is formed on the transistor protectioninsulating film 106.

And, first contact holes 107 a are formed in the first interlayerinsulating film 107 on one impurity diffusion regions 104 c of the MOStransistors 104, and then first contact plugs 108 are buried in thefirst contact holes 107 a.

Then, a first metal film 109, a ferroelectric film 110, and a secondmetal film 111 are formed sequentially on the first contact plugs 108and the first interlayer insulating film 107. As the ferroelectric film110, for example, a PZT film is formed.

Then, as shown in FIG. 1B, capacitors 112 are formed by patterning thefirst metal film 109, the ferroelectric film 110, and the second metalfilm 111 by virtue of the photolithography method.

In the capacitor 112, a lower electrode 109 a is formed of the firstmetal film 109, a dielectric film 110 a is formed of the ferroelectricfilm 110, and an upper electrode 111 a is formed of the second metalfilm 111. The capacitor is the stacked capacitor, and the lowerelectrodes 109 a are connected to one impurity diffusion regions 104 cof the MOS transistors 104 via the underlying first contact plugs 108respectively.

Then, as shown in FIG. 1C, a capacitor protection film 113 is formed onthe capacitors 112 and the first interlayer insulating film 107. Then, asecond interlayer insulating film 114 is formed on the capacitorprotection film 113. Then, a second contact hole 114 a is formed on theother impurity diffusion region 104 d of the MOS transistors 104 bypatterning the second interlayer insulating film 114, the capacitorprotection film 113, the first interlayer insulating film 107, and thetransistor protection insulating film 106 by virtue of thephotolithography method. Then, a second contact plug 115 is formed inthe second contact hole 114 a.

Next, steps required until a structure shown in FIG. 1D is formed willbe explained hereunder.

Third contact holes 114 b are formed on the upper electrodes 110 a ofthe capacitors 112 by patterning the second interlayer insulating film114 and the capacitor protection film 113. Then, a conductive film isformed on the second interlayer insulating film 114 and in the thirdcontact holes 114 b, and then this conductive film is patterned. Thus,wirings 116 a connected to the upper electrodes 111 a of the capacitors112 respectively are formed and simultaneously a conductive pad 116 b isformed on the second contact plug 115.

Then, a third interlayer insulating film 117 is formed on the wirings116 a, the conductive pad 116 b, and the second interlayer insulatingfilm 114. Then, a hole 117 a is formed on the conductive pad 116 b bypatterning the third interlayer insulating film 117. Then, a fourthconductive plug 118 is formed in the hole 117 a.

Then, a bit line 118 connected to the fourth conductive plug 118 isformed on the third interlayer insulating film 117.

As the ferroelectric film 110 of the ferroelectric capacitor 112, forexample, the PZT film is formed. After the formation, this PZT film isannealed in the oxygen atmosphere to crystallize. After the lateretching, the recovery annealing of the PZT film, etc. are carried out inthe oxygen atmosphere.

Here, the situation in which the tungsten plugs are formed as thecontact plug directly under the ferroelectric capacitors shown in FIGS.1A to 1D will be considered.

As set forth in Patent Application Publication (KOKAI) Hei 10-303398,the tungsten plug is oxidized very quickly at a low temperature. Also,oxidation of the tungsten plug spreads throughout the plug once suchoxidation occurs, so that the contact failure is caused easily andreduction in the yield of the FeRAM device is brought about.

Also, even if the polysilicon is employed as the material of the contactplug, such polysilicon is also oxidized though the oxidation is not soserious as the tungsten.

By the way, as explained above, in order to improve the performance ofthe ferroelectric capacitor, the annealing is required in various oxygenatmospheres.

Therefore, improvement in the performance of the ferroelectric capacitorand improvement in the performance of the contact plug were in thetrade-off relationship.

In contrast, various trials were made to prevent the abnormal oxidationof the tungsten plug in the crystallization annealing of theferroelectric film or in the recovery annealing of the ferroelectriccapacitor. For example, in Patent Application Publication (KOKAI) Hei10-303398, Patent Application Publication (KOKAI) 2000-349255, PatentApplication Publication (KOKAI) 2001-44377, Patent ApplicationPublication (KOKAI) Hei 10-150155, and Patent Application Publication(KOKAI) 2000-349252, the structure in which the oxygen barrier-metallayer is formed between the capacitor and the tungsten plug is setforth.

As described above, in the MOS transistor 104 constituting the memorycell, one impurity diffusion region 104 c is connected to theferroelectric capacitor 112 via the contact plug 108, and the otherimpurity diffusion region 104 d is connected to the bit line 119 viaanother contact plug 115.

The reason why the contact plug 115 for bit-line connection is formedafter the ferroelectric capacitor 112 is formed is to prevent theoxidation of the contact plug 115 in the crystallization annealing ofthe ferroelectric film 110 in the oxygen atmosphere or in the recoveryannealing of the ferroelectric capacitor 112.

However, an aspect ratio of the contact plug 115 for bit-line connectionis increased more and more with the further miniaturization in future.Therefore, technical subjects that are to be overcome newly such as theetching to form the contact hole 114 a for bit-line connection, thefilling of the glue layer in the contact hole 114 a for bit-lineconnection, etc. are brought about.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductordevice capable of forming satisfactorily a conductive plug connected toa capacitor and other conductive plugs, and a method of manufacturingthe same.

According to one aspect of the present invention, there is provided asemiconductor device comprising: a first impurity diffusion region and asecond impurity diffusion region formed on a surface layer of asemiconductor substrate; a first insulating layer formed over thesemiconductor substrate; a first hole and a second hole formed in thefirst insulating layer; a first conductive plug formed in the first holeand connected electrically to the first impurity diffusion region; asecond conductive plug formed in the second hole and connectedelectrically to the second impurity diffusion region; an island-likeoxygen-barrier metal layer formed on the first insulating layer over thefirst conductive plug and its peripheral area; an oxidation preventinglayer formed on the first insulating layer and made of material thatprevents oxidation of the second conductive plug; a capacitor having alower electrode formed on the oxygen-barrier metal layer, a dielectriclayer formed on the lower electrode, and an upper electrode formed onthe dielectric layer; a second insulating layer for covering thecapacitor and the oxidation preventing layer; a third hole formed in thesecond insulating layer on the second conductive plug; and a thirdconductive plug formed in the third hole and connected electrically tothe second conductive plug.

The above subject is overcome by providing a semiconductor devicemanufacturing method that comprises the steps of forming a firstimpurity diffusion region and a second impurity diffusion region on asurface layer of a semiconductor substrate; forming a first insulatinglayer over the semiconductor substrate; forming a first hole and asecond hole in the first insulating layer; forming a first conductiveplug, which is connected electrically to the first impurity diffusionregion, in the first hole and simultaneously a second conductive plug,which is connected electrically to the second impurity diffusion region,in the second hole; forming an oxygen-barrier metal layer on the firstconductive plug and the second conductive plug and the first insulatinglayer; patterning the oxygen-barrier metal layer to leave theoxygen-barrier metal layer like an island on the first conductive plug;forming an oxidation preventing layer on the first insulating layer overthe second conductive plug and its peripheral area; forming aninsulating adhesion layer on the oxidation preventing layer and theoxygen-barrier metal layer; exposing an upper surface of theoxygen-barrier metal layer by polishing the insulating adhesion layer;forming a first conductive layer on the oxygen-barrier metal layer andthe insulating adhesion layer; forming a dielectric layer on the firstconductive layer; forming a second conductive layer on the dielectriclayer; forming a capacitor on the oxygen-barrier metal layer over thefirst conductive plug by patterning the second conductive layer, thedielectric layer, and the first conductive layer; forming a secondinsulating layer over the capacitor, the insulating adhesion layer, andthe oxidation preventing layer; forming a third hole over the secondconductive plug by patterning the second insulating layer; and forming athird conductive plug, which is connected electrically to the secondconductive plug, in the third hole.

According to the present invention, the first and second conductiveplugs are formed in the first insulating layer over the semiconductorsubstrate, then the oxygen-barrier metal layer is formed on the firstconductive plug and the oxidation-preventing insulating layer is formedon the second conductive plug, then the capacitor is formed on the firstconductive plug via the oxygen-barrier metal layer, then the secondinsulating layer for covering the capacitor is formed, and then thethird conductive plug is formed on the second conductive plug and in thesecond insulating layer.

Therefore, the structure for connecting the impurity diffusion regionand the upper wiring is made on a via-to-via basis, and it is not neededto form the holes having the large aspect ratio at a time, and thefilling of the holes can be facilitated. As a result, the up-to-dateequipment is not required, and the development cost and the step costcan be reduced.

Also, the oxygen-barrier metal layer is formed on the first insulatinglayer over the first conductive plug and its peripheral area out of thefirst conductive plug and the second conductive plug. Also, theoxidation-preventing insulating layer is formed on the second conductiveplug and the first insulating layer. Therefore, the abnormal oxidationof the first conductive plug is prevented by the oxygen-barrier metallayer, and also the abnormal oxidation of the second conductive plug isprevented by the oxidation-preventing insulating layer. As a result, inthe step of growing the insulating adhesion layer as the underlyinglayer of the capacitor, the step of crystallization annealing of thedielectric layer executed to form the capacitor on the first conductiveplug, and the step of the recovery annealing after formation of thecapacitor, the first and second conductive plugs are never abnormallyoxidized.

In addition, since the oxygen-barrier metal layer and the insulatingadhesion layer are planarized simultaneously by the polishing, thecapacitor lower electrode formed on the oxygen-barrier metal layer isformed flat. Thus, generation of the degradation of the dielectric layerformed on the lower electrode is avoided, and also formation of thecapacitor with good characteristics can be formed.

Also, the third conductive plug is formed in the second insulating layerfor covering the capacitor to connect the third conductive plug and thesecond conductive plug. Thus, the abnormal oxidation of the secondconductive plug can be avoided until the third conductive plug is formedafter the oxidation-preventing insulating layer is formed. In otherwords, since the oxidation-preventing insulating layer is present aroundthe second conductive plug, the entering of the oxygen from the uppersurface of the interlayer insulating layer is prevented and thus theoxidation of the second conductive plug is prevented much more. In thiscase, since the step of the oxygen annealing is not contained in thesteps executed from the formation of the first and second conductiveplugs to the formation of the insulating adhesion layer, the abnormaloxidation of the first and second conductive plugs is not caused priorto the formation of the oxidation-preventing insulating layer.

Further, according to the present invention, the oxygen-barrier metallayer instead of the oxidation-preventing insulating layer is formedlike the island on the second conductive plug. Therefore, not only thesame advantages as the oxidation-preventing insulating layer is obtainedbut also the step of forming the oxidation-preventing insulating layeris omitted. In this case, the oxygen-barrier metal layer formed like theisland on the first and second conductive plugs respectively can beformed simultaneously, and thus the number of steps is never increased.

Also, the oxidation-preventing layer made of the same material as theoxygen-barrier metal layer is formed on the second conductive plug andits peripheral area and, in addition, side surfaces of theoxygen-barrier metal layer formed on the first and second conductiveplugs respectively are covered with the oxidation-preventing insulatinglayer. Therefore, the oxygen is prevented from entering from theclearance between the oxygen-barrier metal layer and the firstinsulating layer, and also the oxidation of the first and secondconductive plugs is prevented.

In this case, the step of patterning the lower electrode is reduced, byadopting the oxygen-barrier metal layer formed on the first conductiveplug under the capacitor as the lower electrode.

The peeling-off of the capacitor lower electrode is prevented, byforming the conductive adhesion layer between the conductive layerconstituting the capacitor lower electrode and the oxygen-barrier metallayer.

The adherence between the oxygen-barrier metal layer and the firstinsulating layer is improved, by forming the conductive adhesion layerbetween the oxygen-barrier metal layer and the first insulating layer.Therefore, the oxygen is prevented without fail from being supplied fromthe clearance between the oxygen-barrier metal layer and the firstinsulating layer to the conductive plug.

Further, when the oxygen-barrier metal layer is formed as themulti-layered structure and the upper layer is formed of the materialthat can be relatively easily polished, e.g., iridium oxide, theunderlying layer of the capacitor is formed flatter by polishing theinsulating adhesion layer and the oxygen-barrier metal layer. Therefore,the characteristic of the capacitor is improved.

In the case that the oxygen-barrier metal layer is patterned by usingthe hard mask, the insulating adhesion layer is formed on the hard maskand the oxidation-preventing insulating layer after the patterning ofthe oxygen-barrier metal layer, and then the insulating adhesion layerand the hard mask is polished continuously until the oxygen-barriermetal layer is exposed. Therefore, the independent step of removing thehard mask is omitted. In addition, since the second conductive plug iscovered with the insulating adhesion layer in removing the hard mask,the damage of the second conductive plug in removing the hard mask isavoided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1D are sectional views showing steps of forming thesemiconductor device in the prior art;

FIGS. 2A to 2O are sectional views showing steps of manufacturing asemiconductor device according to a first embodiment of the presentinvention;

FIGS. 3A to 3I are sectional views showing steps of manufacturing asemiconductor device according to a second embodiment of the presentinvention;

FIGS. 4A to 4E are sectional views showing steps of manufacturing asemiconductor device according to a third embodiment of the presentinvention;

FIGS. 5A to 5G are sectional views showing steps of manufacturing asemiconductor device according to a fourth embodiment of the presentinvention;

FIG. 6 is a sectional view showing steps of manufacturing anothersemiconductor device according to the fourth embodiment of the presentinvention;

FIGS. 7A to 7I are sectional views showing steps of manufacturing asemiconductor device according to a fifth embodiment of the presentinvention;

FIG. 8 is a plan view showing an alignment mark in the semiconductorwafer;

FIG. 9 is a plan view showing another alignment mark in thesemiconductor wafer;

FIGS. 10A to 10I are sectional views showing steps of manufacturing asemiconductor device according to a sixth embodiment of the presentinvention;

FIG. 11 is a sectional view showing another semiconductor deviceaccording to the sixth embodiment of the present invention;

FIGS. 12A to 12G are sectional views showing steps of manufacturing asemiconductor device according to a seventh embodiment of the presentinvention;

FIG. 13 is a sectional view showing another semiconductor deviceaccording to the seventh embodiment of the present invention; and

FIGS. 14A to 14G are sectional views showing steps of manufacturing asemiconductor device according to an eighth embodiment of the presentinvention; and

FIGS. 15A to 15D are sectional views showing steps of manufacturing asemiconductor device according to a ninth embodiment of the presentinvention; and

FIGS. 16A to 16C are sectional views showing steps of manufacturing asemiconductor device in which an interval between the capacitors is innarrow according to a comparative example; and

FIG. 17 is a plane view showing memory cell region in a semiconductordevice according to embodiment of the present invention; and

FIGS. 18A to 18G are sectional views showing steps of manufacturing asemiconductor device according to a tenth embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be explained in detail withreference to the drawings hereinafter.

First Embodiment

FIGS. 2A to 2O are sectional views showing steps of manufacturing asemiconductor device according to a first embodiment of the presentinvention.

Next, steps required until a sectional structure shown in FIG. 2A isformed will be explained hereunder.

First, an element isolation recess is formed around a transistor formingregion of an n-type or p-type silicon (semiconductor) substrate 1 by thephotolithography method, and then an element isolation insulating layer2 is formed by burying silicon oxide (SiO₂) in the element isolationrecess. The element isolation insulating layer 2 having such structureis called STI (Shallow Trench Isolation). In this case, an insulatinglayer formed by the LOCOS (Local Oxidation of Silicon) method may beemployed as the element isolation insulating layer.

Then, a p-type well 1 a is formed by introducing the p-type impurityselectively into the transistor forming region of the silicon substrate1 in the memory cell region.

Then, a silicon oxide layer as a gate insulating layer 3 is formed bythermally oxidizing a surface of the p-type well 1 a of the siliconsubstrate 1.

Then, an amorphous silicon or polysilicon layer and a tungsten silicidelayer are formed sequentially on an overall upper surface of the siliconsubstrate 1. Then, gate electrodes 4 a, 4 b are formed on the p-typewell la in the memory cell region by patterning the silicon layer andthe tungsten silicide layer by virtue of the photolithography method.These gate electrodes 4 a, 4 b are formed on the silicon substrate 1 viathe gate insulating layer 3.

In this case, in the memory cell region, two gate electrodes 4 a, 4 bare formed on one p-type well la in parallel and these gate electrodes 4a, 4 b constitute a part of the word line.

Then, first to third n-type impurity diffusion regions 5 a to 5 cserving as the source/drain are formed by ion-implanting the n-typeimpurity, e.g., phosphorus, into the p-type well 1 a on both sides ofthe gate electrodes 4 a, 4 b.

Then, an insulating layer, e.g., a silicon oxide (SiO₂) layer is formedon the overall surface of the silicon substrate 1 by the CVD method.Insulating sidewall spacers 6 are left on both side portions of the gateelectrodes 4 a, 4 b by etching back the insulating layer.

Then, in the p-type well 1 a, the n-type impurity is ion-implanted onceagain into the first to third n-type impurity diffusion regions 5 a to 5c by using the gate electrodes 4 a, 4 b and the sidewall spacers 6 as amask. Thus, high-concentration impurity regions are formed in the firstto third n-type impurity diffusion regions 5 a to 5 c respectively.

In this case, in one p-type well 1 a, the first n-type impuritydiffusion region 5 a formed between two gate electrodes 4 a, 4 b isconnected electrically to the bit line to be described later, and alsothe second and third n-type impurity diffusion regions 5 b, 5 c formednear both end sides of the p-type well 1 a are connected electrically tothe capacitor lower electrodes to be described later.

According to the above steps, two n-type MOS transistors T₁, T₂ havingthe gate electrodes 4 a, 4 b and the n-type impurity diffusion regions 5a to 5 c of the LDD structure are formed in the p-type well 1 a whileusing one n-type impurity diffusion region 5 a commonly.

Then, as a cover layer 7 for covering the MOS transistors T₁, T₂, asilicon oxide nitride (SiON) layer of about 200 nm thickness is formedon the overall surface of the silicon substrate 1 by the plasma CVDmethod. Then, a silicon oxide (SiO₂) layer of about 1.0 μm thickness isformed as a first interlayer insulating layer 8 on the cover layer 7 bythe plasma CVD method using the TEOS gas.

Then, the first interlayer insulating layer 8 is annealed at thetemperature of 700° C. for 30 minutes in the nitrogen atmosphere at theatmospheric pressure, for example, whereby the first interlayerinsulating layer 8 is densified. Then, an upper surface of the firstinterlayer insulating layer 8 is planarized by the CMP (ChemicalMechanical Polishing) method.

Then, as shown in FIG. 2B, the first interlayer insulating layer 8 andthe cover layer 7 are etched by using a resist pattern (not shown).Thus, first, second, and third contact holes 8 a, 8 b, 8 c are formed onthe first, second, and third n-type impurity diffusion regions 5 a, 5 b,5 c in the memory cell region respectively.

Next, steps required until a structure shown in FIG. 2C is formed willbe explained hereunder.

First, a titanium (Ti) layer of 20 nm thickness and a titanium nitride(TiN) layer of 50 nm thickness are formed sequentially as a glue layer 9a on the first interlayer insulating layer 8 and in the first to thirdcontact holes 8 a to 8 c by the sputter method. Then, a tungsten (W)layer 9 b is grown on the glue layer 9 a by the CVD method using WF₆ tofill perfectly insides of the contact holes 8 a to 8 c.

Then, the tungsten layer 9 b and the glue layer 9 a are polished by theCMP method to remove from an upper surface of the first interlayerinsulating layer 8. As a result, the tungsten layer 9 b and the gluelayer 9 a being left in the first, second, and third contact holes 8 a,8 b, 8 c respectively are used as first, second, and third conductiveplugs 10 a, 10 b, 10 c. The first, second, and third conductive plugs 10a, 10 b, 10 c are connected to the first, second, and third n-typeimpurity diffusion regions 5 a, 5 b, 5 c respectively. Also, the firstconductive plug 10 a is connected electrically to the bit line to bedescribed later, and the second and third conductive plugs 10 b, 10 care connected electrically to the capacitors to be described laterrespectively.

Then, the first interlayer insulating layer 8 is exposed to the nitrogenplasma at the substrate temperature of 350° C. for 120 seconds.

Then, as shown in FIG. 2D, an iridium layer is formed as a conductiveoxygen-barrier metal layer 11 on the first to third conductive plugs 10a to 10 c and the first interlayer insulating layer 8 by the sputter.The iridium layer is formed to have a thickness enough to prevent theabnormal oxidation of the second and third conductive plugs 10 b, 10 c.In order to prevent the abnormal oxidation of the conductive plugs 10 ato 10 c caused when the annealing is carried out at the substratetemperature of 550° C. in the oxygen-containing atmosphere, the iridiumlayer is formed to have the thickness of 200 nm, for example, and isalso formed to increase such thickness by 100 nm every time when thesubstrate temperature is increased by 100° C.

Then, resist patterns are formed as a mask M₁ on the oxygen-barriermetal layer 11 over the second and third conductive plugs 10 b, 10 c andtheir peripheral regions.

Then, as shown in FIG. 2E, the oxygen-barrier metal layer 11 in theregion that is not covered with the mask M₁ is etched, and thus theoxygen-barrier metal layers 11 are left like an island on the second andthird conductive plugs 10 b, 10 c and their peripheral regions.Accordingly, the first conductive plug 10 a is exposed. Then, the masksM₁ are removed. In this case, a hard mask made of titanium nitride,silicon oxide, or the like may be employed as the mask M₁. The hard maskconsists of inorganic material, unlike the resist mask made of organicmaterial.

Then, as shown in FIG. 2F, a silicon oxide nitride (SiON) layer or asilicon nitride (Si₃N₄) layer is formed as an oxidation-preventinginsulating layer 12 on the first conductive plug 10 a, theoxygen-barrier metal layers 11, and the first interlayer insulatinglayer 8 by the CVD method to have a thickness of 100 nm, for example.The SiON layer or the Si₃N₄ layer of 100 nm thickness has such acapability that is able to prevent the oxidation of the first conductiveplug 10 a in the oxygen annealing at about 65020 C.

Then, an insulating adhesion layer 13 is formed on theoxidation-preventing insulating layer 12. The insulating adhesion layer13 is formed to improve the adhesion to the capacitor lower electrode tobe described later. As the insulating adhesion layer 13, a silicon oxide(SiO₂) layer of 100 nm thickness is formed by the CVD method using TEOS,for example.

Then, as shown in FIG. 2G, while making the oxygen-barrier metal layers11 function as a stopper layer, the insulating adhesion layer 13 and theoxidation-preventing insulating layer 12 are polished by the CMP methodto expose an upper surface of the oxygen-barrier metal layers 11. Inthis case, polished surfaces of the oxygen-barrier metal layers 11, theinsulating adhesion layer 13, and the oxidation-preventing insulatinglayer 12 are made flat.

Then, as shown in FIG. 2H, a first conductive layer 14 is formed on theoxygen-barrier metal layers 11, the oxidation-preventing insulatinglayer 12, and the insulating adhesion layer 13. As the first conductivelayer 14, an iridium (Ir) layer 14 w of 200 nm thickness, an iridiumoxide (IrO₂) layer 14 x of 30 nm thickness, a platinum oxide (PtO) layer14 y of 30 nm thickness, and a platinum (Pt) layer 14 z of 50 nmthickness, for example, are formed in sequence by the sputter.

In this case, the insulating adhesion layer 13 is annealed to preventthe peeling-off of the layer, for example, before or after the firstconductive layer 14 is formed. As the annealing method, RTA (RapidThermal Annealing) executed at 750° C. for 60 second in the argonatmosphere, for example, may be employed.

Then, a PZT layer of 200 nm thickness, for example, is formed as aferroelectric layer 15 on the first conductive layer 14 by the sputtermethod. As the method of forming the ferroelectric layer 15, there arethe MOD (Metal Organic Deposition) method, the MOCVD (Metal Organic CVD)method, the sol-gel method, etc. in addition to this. Also, as thematerial of the ferroelectric layer 15, other PZT material such asPLCSZT, PLZT, etc., the Bi-layered structure compound material such asSrBi₂Ta₂O₉, SrBi₂(Ta,Nb)₂O₉, etc., and other metal oxide ferroelectricsubstance may be employed in addition to PZT.

Then, the ferroelectric layer 15 is annealed in the oxygen-containingatmosphere to crystallize. As such annealing, two-step RTA processhaving the first step that is executed at the substrate temperature of600° C. for 90 second in the mixed-gas atmosphere containing argon (Ar)and oxygen (O₂) and the second step that is executed at the substratetemperature of 750° C. for 60 second in the oxygen atmosphere, forexample, is employed.

An iridium oxide (IrO₂) of 200 nm thickness, for example, is formed as asecond conductive layer 16 on the ferroelectric layer 15 by the sputtermethod.

Then, a TiN layer and a SiO₂ layer are formed in sequence as a hard mask17 on the second conductive layer 16. The TiN layer is formed by thesputter, and the SiO₂ layer is formed by the CVD method using TEOS. Thehard masks 17 are patterned into the capacitor planar shape over theoxygen-barrier metal layers 11 and their peripheries by thephotolithography method.

Then, the second conductive layer 16, the ferroelectric layer 15, andthe first conductive layer 14 in the region that is not covered with thehard masks 17 are etched sequentially. Thus, the capacitors Q are formedon the oxygen-barrier metal layers 11, the insulating adhesion layer 13,and the oxidation-preventing insulating layer 12. In this case, thesecond conductive layer 16, the ferroelectric layer 15, and the firstconductive layer 14 are etched by the sputter reaction in the atmospherecontaining a halogen element.

As shown in FIG. 2I, each of the capacitors Q consists of a lowerelectrode 14 a made of the first conductive layer 14, a dielectric layer15 a made of the ferroelectric layer 15, and an upper electrode 16 amade of the second conductive layer 16.

Two capacitors Q are formed over one well 1 a. The lower electrodes 14 aof the capacitors Q are connected electrically to the second or thirdn-type impurity diffusion region 5 b, 5 c via the second or thirdconductive plug 10 b, 10 c respectively.

In this case, if the insulating adhesion layer 13 is etched in formingthe capacitors Q, the underlying oxidation-preventing insulating layer12 functions as the etching stopper, and thus the first conductive plug10 a is never exposed.

The hard masks 17 are removed after patterns of the capacitors Q areformed.

Then, in order to recover the damage of the ferroelectric layer 15caused by the etching, the recovery annealing of the capacitors Q isexecuted. The recovery annealing in this case is carried out at thesubstrate temperature of 650° C. for 60 minutes in the furnacecontaining the oxygen, for example.

In this manner, when the annealing process such as the recoveryannealing or the like is applied immediately after the patterning of theferroelectric layer 15 is executed, the thermal resistance of the secondand third conductive plugs 10 b, 10 c formed directly under the lowerelectrodes 14 a is decided by the oxygen permeability of theoxygen-barrier metal layers 11 and also the oxidation resistance of thefirst conductive plug 10 a not positioned directly under the lowerelectrodes 14 a is decided by the oxygen permeability of the insulatingadhesion layer 13 and the oxidation-preventing insulating layer 12.

Although the above-mentioned thermal processes are required to form thecapacitors Q, the first conductive plug 10 a made of tungsten is notabnormally oxidized in the condition of which the thickness of thesilicon nitride layer used as the insulating adhesion layer 13 is set to70 nm.

Also, assume that the iridium layer of 200 nm thickness is present onthe second and third conductive plugs 10 b, 10 c made of tungsten, thesecond and third conductive plugs 10 b, 10 c are abnormally oxidized bythe above oxygen annealing to cause the contact failure. Experimentallythe thickness of the Ir layer as the oxygen-barrier metal layer 11 mustbe further increased by 100 nm to increase the annealing temperature by100° C. For example, in order to form the tungsten plug, which can standthe thermal process, directly under the lower electrodes 14 a, theoxygen-barrier metal layer made of Ir having a thickness of more than400 nm must be formed. In this embodiment, a total thickness of the Irlayer, which consists of the iridium layer constituting theoxygen-barrier metal layers 11 and the iridium layer 14 z constitutingthe first conductive layer 14, is set to 400 nm. Thus, the abnormaloxidation of the second and third conductive plugs 10 b, 10 c areprevented.

Then, as shown in FIG. 2J, alumina of 50 nm thickness is formed as acapacitor protection layer 18 on the capacitors Q and the insulatingadhesion layer 13 by the sputter. This capacitor protection layer 18protects the capacitors Q from the process damage, and may be formed ofPZT in addition to alumina. Then, the capacitors Q are annealed at 650°C. for 60 minute in the oxygen atmosphere in the furnace.

Then, a silicon oxide (SiO₂) of about 1.0 μm thickness is formed as asecond interlayer insulating layer 19 on the capacitor protection layer18 by the plasma CVD method using the HDP (High Density Plasma)equipment.

Then, an upper surface of the second interlayer insulating layer 19 isplanarized by the CMP method. In this example, a remaining thickness ofthe second interlayer insulating layer 19 after CMP is set to almost 300nm on the upper electrodes 16 a.

Then, as shown in FIG. 2K, the second interlayer insulating layer 19,the capacitor protection layer 18, the insulating adhesion layer 13, andthe oxidation-preventing insulating layer 12 are etched by using aresist mask (not shown). Thus, a fourth contact hole 19 a is formed onthe first conductive plug 10 a.

Then, as shown in FIG. 2L, a TiN layer of 50 nm thickness is formed as aglue layer 20 a in the fourth contact hole 19 a and on the secondinterlayer insulating layer 19 by the sputter method. Then, a tungstenlayer 20 b is grown on the glue layer 20 a by the CVD method to buryperfectly the inside of the fourth contact hole 19 a.

Then, as shown in FIG. 2M, the tungsten layer 20 b and the glue layer 20a are polished by the CMP method to remove from an upper surface of thesecond interlayer insulating layer 19. Then, the tungsten layer 20 b andthe glue layer 20 a left in the fourth contact hole 19 a are used as afourth conductive plug 21.

Accordingly, the fourth conductive plug 21 is connected to the firstconductive plug 10 a to form the via-to-via contact, and is connectedelectrically to the first impurity diffusion region 5 a.

Then, the second interlayer insulating layer 19 is annealed at 350° C.for 120 seconds in the nitrogen plasma atmosphere.

Then, as shown in FIG. 2N, a SiO₂ layer of 100 nm thickness is formed asa second oxidation-preventing insulating layer 22 on the fourthconductive plug 21 and the second interlayer insulating layer 19 by theCVD method.

Then, holes 23 are formed on the upper electrodes 16 a of the capacitorsQ by patterning the second oxidation-preventing insulating layer 22, thesecond interlayer insulating layer 19, and the capacitor protectionlayer 18 by means of the photolithography method. The capacitors Q thatare subjected to the damage by forming the holes 23 are recovered by theannealing. Such annealing is carried out at the substrate temperature of550° C. for 60 minutes in the oxygen-containing atmosphere, for example.

Next, steps required until a structure shown in FIG. 20 is formed willbe explained hereunder.

First, the second oxidation-preventing insulating layer 22 formed on thesecond interlayer insulating layer 19 is removed by the etching-back.Thus, a surface of the fourth conductive plug 21 is exposed.

Then, a multi-layered metal layer is formed in the holes 23 on the upperelectrodes 16 a of the capacitors Q and on the second interlayerinsulating layer 19. As the multi-layered metal layer, a Ti layer of 60nm thickness, a TiN layer of 30 nm thickness, an Al—Cu layer of 400 nmthickness, a Ti layer of 5 nm thickness, and a TiN layer of 70 nmthickness are formed sequentially.

Then, a conductive pad 24 a, which is connected to the fourth conductiveplug 21, and first-layer metal wirings 24 b, 24 c, which are connectedto the upper electrodes 16 a via the holes 23, are formed by patterningthe multi-layered metal layer.

In this case, in order to prevent the reduction of the pattern precisionby the reflection of the exposure light upon patterning of themulti-layered metal layer, the method of forming a reflection preventinglayer (not shown) made of silicon oxide nitride (SiON), or the like onthe multi-layered metal layer to have a thickness of 30 nm, then formingresist patterns such as wiring shapes, etc. by coating a resist on thereflection preventing layer and exposing/developing the resist, and thenetching the multi-layered metal layer by using the resist patterns isemployed. The reflection preventing layer may be left as it is after thepatterning of the multi-layered metal layer.

Then, a third interlayer insulating layer 25 is formed on the secondinterlayer insulating layer 19, the first-layer metal wirings 24 b, 24c, and the conductive pad 24 a.

Then, a bit-line contact hole 25 a is formed on the conductive pad 24 aby patterning the third interlayer insulating layer 25. Also, a fifthconductive plug 26 made of a TiN layer and a W layer sequentially fromthe bottom is formed in the hole 25 a.

Then, a second-layer metal wiring containing a bit line 27 is formed onthe third interlayer insulating layer 25. The bit line 27 has themulti-layered metal structure, like the first-layer metal wirings 24 b,24 c. Also, when the bit line 27 is connected to the fifth conductiveplug 26, such bit line 27 is connected electrically to the first n-typeimpurity diffusion region 5 a via the conductive pad 24 a, the fourthconductive plug 21, and the first conductive plug 10 a.

Then, an insulating layer for covering the second-layer metal wiring,etc. are formed, and finally a cover layer made of a TEOS materialsilicon oxide layer and a silicon nitride layer is formed. But theirdetails will be omitted herein.

In the above embodiment, under the lower electrodes 14 a constitutingthe capacitors Q, the second and third conductive plugs 10 b, 10 c arecovered with the oxygen-barrier metal layer 11 and also the firstconductive plug 10 a and the first interlayer insulating layer 8, whichare connected to the bit line 27, are covered with theoxidation-preventing insulating layer 12. Hence, in the crystallizationannealing and the recovery annealing of the ferroelectric layer 15, theabnormal oxidation of the first conductive plug 10 a is prevented by theoxidation-preventing insulating layer 12 and also the abnormal oxidationof the second and third conductive plugs 10 b, 10 c are prevented by theoxygen-barrier metal layer 11. Also, since the oxidation-preventinginsulating layer 12 still covers the first conductive plug 10 a untilthe fourth contact hole 19 a is formed, the first conductive plug 10 ais never oxidized by the annealing applied in the formation of thecapacitors Q and later steps. In addition, in the case that the secondinterlayer insulating layer 19 is formed over the first conductive plug10 a, the first conductive plug 10 a is prevented from being oxidizedsince the first conductive plug 10 a is covered with theoxidation-preventing insulating layer 12.

In addition, patterned side surfaces of the oxygen-barrier metal layer11 are covered with the oxidation-preventing insulating layer 12.Therefore, if the size of the oxygen-barrier metal layer 11 is formedsubstantially identically to the second and third conductive plugs 10 b,10 c, the oxygen is prevented from entering into the oxygen-barriermetal layer 11 from the side and thus the abnormal oxidation of thesecond and third conductive plugs 10 b, 10 c is never caused.

The oxygen-barrier metal layer 11 formed on the second and thirdconductive plugs 10 b, 10 c respectively functions as a stopper when theoxidation-preventing insulating layer 12 and the insulating adhesionlayer 13 are polished by the CMP method. As a result, upper surfaces ofthe oxygen-barrier metal layer 11, the oxidation-preventing insulatinglayer 12, and the insulating adhesion layer 13 are made flat, and thusdegradation of the crystal of the ferroelectric layer 15 formed on thefirst conductive layer 14 is prevented.

Also, since the FeRAM has level difference on the first interlayerinsulating layer 8 by the ferroelectric capacitor rather than the normallogic product, it is possible that an aspect ratio of the contact holefrom the first-layer metal wiring 24 b to the first n-type impuritydiffusion region 5 a is increased. If it is tried to form this contacthole by the etching at one step like the prior art shown in FIG. 1A to1C, not only the etching itself becomes difficult but also the fillingof the glue layer into the contact hole becomes severe. The up-to-dateequipment is needed to eliminate such problem.

In contrast, like the present embodiment, the via-to-via contact isformed between the first n-type impurity diffusion region 5 a and thecontact pad 24 a via two conductive plugs 21, 10 a. As a result, notonly yield of the FeRAM product can be increased but also the existingequipment can be still employed, so that there can be achieved such anadvantage that reduction in the development cost and the step cost canbe implemented.

Second Embodiment

In the first embodiment, the iridium layer formed on the second andthird conductive plugs 10 b, 10 c as the oxygen-barrier metal layer 11and the iridium layer 14 w formed as the lowermost layer portion of thelower electrode 14 a of the capacitor Q are formed by separate steps.

Therefore, in the present embodiment, a structure in which one of twoiridium layers is omitted will be explained hereunder.

FIGS. 3A to 3I are sectional views showing steps of manufacturing asemiconductor device according to a second embodiment of the presentinvention.

First, as shown in FIG. 3A, in compliance with the steps shown in thefirst embodiment, the MOS transistors T₁, T₂ are formed on the siliconsubstrate 1 and then the cover layer 7, the first interlayer insulatinglayer 8, and the first to third conductive plugs 10 a to 10 c areformed.

Then, as shown in FIG. 3B, the iridium layer is formed as a conductiveoxygen-barrier metal layer 11 a on the first to third conductive plugs10 a to 10 c and the first interlayer insulating layer 8 by the sputter.The oxygen-barrier metal layer 11 a constitutes a part of the lowerelectrode of the capacitor Q, as described later.

The iridium layer acting as the oxygen-barrier metal layer 11 a isformed to have a thickness enough to prevent the abnormal oxidation ofthe first to third conductive plugs 10 a to 10 c. For instance, in orderto prevent the abnormal oxidation of the first to third conductive plugs10 a to 10 c in the annealing at the substrate temperature of 550° C. inthe oxygen-containing atmosphere, such iridium layer is formed to have athickness of 200 nm, for example, and also is formed to add thethickness by 100 nm every time when the substrate temperature isincreased by 100° C. In other words, when the iridium layer has thethickness of 400 nm, the iridium layer can prevent the oxidation of thefirst to third conductive plugs 10 a to 10 c from the oxygen annealingat 750° C.

Then, masks M₂ are formed on the oxygen-barrier metal layer 11 a overthe second and third conductive plugs 10 b, 10 c and their peripheralareas. A planar shape of the mask M₂ is set equal to the shape of thelower electrode of the capacitor. As the mask M₂, a hard mask made oftitanium nitride, silicon oxide, or the like may be employed.

Then, as shown in FIG. 3C, the oxygen-barrier metal layer 11 a in theregion that is not covered with the masks M₂ is etched. Thus, theoxygen-barrier metal layer 11 a is left on the second and thirdconductive plugs 10 b, 10 c and their peripheral areas to have a size ofthe capacitor. As the etching gas of the oxygen-barrier metal layer 11a, a halogen gas is used. Now, the first conductive plug 10 a isexposed.

Then, the masks M₂ are removed.

Then, as shown in FIG. 3D, the silicon oxide nitride (SiON) layer or thesilicon nitride (Si₃N₄) layer of 100 nm thickness, for example, isformed as the oxidation-preventing insulating layer 12 on the firstconductive plug 10 a, the oxygen-barrier metal layer 11 a, and the firstinterlayer insulating layer 8 by the CVD method. Then, the silicon oxide(SiO₂) layer of 300 nm thickness, for example, is formed as theinsulating adhesion layer 13 on the oxidation-preventing insulatinglayer 12 by the CVD method using TEOS, for example.

Then, as shown in FIG. 3E, an upper surface of the oxygen-barrier metallayer 11 a is exposed by polishing the insulating adhesion layer 13 andthe oxidation-preventing insulating layer 12 by means of the CMP methodwhile causing the oxygen-barrier metal layer 11 a to function as thestopper layer. In this case, upper surfaces of the oxygen-barrier metallayer 11 a, the insulating adhesion layer 13, and theoxidation-preventing insulating layer 12 are made flat by the CMPmethod.

Then, as shown in FIG. 3F, a IrO₂ layer 14 x of 30 nm thickness, a PtOlayer 14 y of 30 nm thickness, and a Pt layer 14 z of 50 nm thickness,for example, are formed in sequence as a first conductive layer 14 b onthe oxygen-barrier metal layer 11 a, the oxidation-preventing insulatinglayer 12, and the insulating adhesion layer 13 by the sputter.

In this case, the insulating adhesion layer 13 is annealed to preventthe peeling-off of the layer, for example, before or after the firstconductive layer 14 b is formed. As the annealing method, RTA (RapidThermal Annealing) executed at 750° C. for 60 second in the argonatmosphere, for example, may be employed.

Then, the PZT layer of 200 nm thickness, for example, is formed as theferroelectric layer 15 on the first conductive layer 14 b by the sputtermethod. As the method of forming the ferroelectric layer 15, there arethe MOD method, the MOCVD method, the sol-gel method, etc. in additionto this. Also, as the material of the ferroelectric layer 15, other PZTmaterial such as PLCSZT, PLZT, etc., the Bi-layered structure compoundmaterial such as SrBi₂Ta₂O₉, SrBi₂(Ta,Nb)₂O₉, etc., and other metaloxide ferroelectric substance may be employed in addition to PZT.

Then, the ferroelectric layer 15 is annealed in the oxygen-containingatmosphere to crystallize. As such annealing, two-step RTA processhaving the first step that is executed at the substrate temperature of600° C. for 90 seconds in the mixed-gas atmosphere consisting of Ar andO₂ and the second step that is executed at the substrate temperature of750° C. for 60 seconds in the oxygen atmosphere, for example, isemployed.

Then, the IrO₂ layer of 200 nm thickness, for example, is formed as thesecond conductive layer 16 on the ferroelectric layer 15 by the sputtermethod.

Then, the TiN layer and the SiO₂ layer are formed in sequence as thehard mask 17 on the second conductive layer 16. The TiN layer is formedby the sputter, and the SiO₂ layer is formed by the CVD method usingTEOS. The hard masks 17 are patterned into the planar shape, which isalmost same as the oxygen-barrier metal layers 11 a, over the second andthird conductive plugs 10 b, 10 c.

Then, the second conductive layer 16, the ferroelectric layer 15, andthe first conductive layer 14 b in the region that is not covered withthe hard masks 17 are etched sequentially. In this case, the secondconductive layer 16, the ferroelectric layer 15, and the firstconductive layer 14 b are etched by the sputter reaction in theatmosphere containing the halogen element. Here, since theoxidation-preventing insulating layer 12 functions as the etchingstopper even after the insulating adhesion layer 13 is etched by suchetching, the first conductive plug is never exposed.

According to the above, as shown in FIG. 3G, the capacitors Q are formedon the first interlayer insulating layer 8. The lower electrode 14 a ofthe capacitor Q is made of the first conductive layer 14 b and theoxygen-barrier metal layers 11 a. Also, the dielectric layer 15 a of thecapacitor Q is made of the ferroelectric layer 15. Also, the upperelectrode 16 a of the capacitor Q is made of the second conductive layer16.

Two capacitors Q are arranged over one well 1 a. These lower electrodes14 a are connected electrically to the second or third n-type impuritydiffusion region 5 b, 5 c via the second or third conductive plug 10 b,10 c respectively.

In this case, since a layer thickness of the first conductive layer 14 bto be etched is thin rather than the first conductive layer 14 in thefirst embodiment, the hard masks 17 can be formed thinner than the firstembodiment.

The hard masks 17 are removed after patterns of the capacitors Q areformed.

Then, in order to recover the damage of the ferroelectric layer 15caused by the etching, the recovery annealing of the capacitors Q isexecuted. The recovery annealing in this case is carried out at thesubstrate temperature of 650° C. for 60 minutes in the furnacecontaining the oxygen, for example.

In this manner, when the annealing process such as the recoveryannealing or the like is applied immediately after the patterning of theferroelectric layer 15 is executed, the thermal resistance of the secondand third conductive plugs 10 b, 10 c formed directly under the lowerelectrodes 14 a is decided by the oxygen permeability of theoxygen-barrier metal layers 11 a, and also the oxidation resistance ofthe first conductive plug 10 a not positioned directly under the lowerelectrodes 14 a is decided by the oxygen permeability of the insulatingadhesion layer 13 and the oxidation-preventing insulating layer 12.

Although the above thermal processes are required to form the capacitorsQ, the first conductive plug 10 a made of tungsten is not abnormallyoxidized by condition of which the thickness of the silicon nitridelayer used as the insulating adhesion layer 13 is set to 70 nm.

Also, in the condition of the iridium layer of 400 nm thickness formedon the second and third conductive plugs 10 b, 10 c made of tungsten,the abnormal oxidation of the second and third conductive plugs 10 b, 10c is not caused by the oxygen annealing.

Then, as shown in FIG. 3H, the alumina of 50 nm thickness is formed asthe capacitor protection layer 18 on the capacitors Q, theoxidation-preventing insulating layer 12, and the insulating adhesionlayer 13 by the sputter. This capacitor protection layer 18 protects thecapacitors Q from the process damage, and may be formed of PZT inaddition to the alumina. Then, the capacitors Q are annealed at 650° C.for 60 minutes in the oxygen atmosphere in the furnace.

Then, as shown in FIG. 3I, in compliance with the steps shown in thefirst embodiment, the fourth conductive plug 21, the conductive pad 24a, the first-layer metal wirings 24 b, 24 c, the third interlayerinsulating layer 25, the fifth conductive plug 26, the bit line 27, etc.are formed.

As described above, in the present embodiment, the oxygen-barrier metallayer 11 a constituting the lowermost layer of the lower electrodes 14 aof the capacitors Q is formed previously over the second and thirdconductive plugs 10 b, 10 c to have the lower electrode shape, then theoxidation-preventing insulating layer 12 and the insulating adhesionlayer 13 are formed, then the oxygen-barrier metal layer 11 a is exposedby polishing the oxidation-preventing insulating layer 12 and theinsulating adhesion layer 13 by virtue of the CMP method, and thenremaining metal layers of the lower electrodes 14 a are formed on theoxygen-barrier metal layers 11 a. Here, the iridium layer, for example,is formed as the oxygen-barrier metal and lower electrode.

In the first embodiment, the iridium layers constituting theoxygen-barrier metal layer and the lower electrode respectively areformed by separate steps and patterned separately. In the presentembodiment, the iridium layer is formed by one layer forming step andone patterning step, and therefore there is such a merit that a part ofsteps of forming the lower electrodes can be reduced.

By the way, like the first embodiment, in the crystallization annealingof the ferroelectric layer 15 and the recovery annealing after theformation of the capacitors Q, the abnormal oxidation of the second andthird conductive plugs 10 b, 10 c is prevented by the oxygen-barriermetal layers 11 a and also the abnormal oxidation of the firstconductive plug 10 a is prevented by the oxidation-preventing insulatinglayer 12.

In addition, since upper surfaces of the oxygen-barrier metal layers 11a, the oxidation-preventing insulating layer 12, and the insulatingadhesion layer 13 are planarized by the CMP method, the first conductivelayer 14 b formed on the oxygen-barrier metal layers 11 a, theoxidation-preventing insulating layer 12, and the insulating adhesionlayer 13 becomes flat in the neighborhood of the oxygen-barrier metallayers 11 a. Thus, degradation of the crystal of the ferroelectric layer15 formed on the first conductive layer 14 b is prevented.

Also, the conductive plugs 10 a, 21 for the bit-line contact are formedseparately in the first interlayer insulating layer 8 and the secondinterlayer insulating layer 19. As a result, not only the yield of theFeRAM product can be increased but also the existing equipment can bestill employed, so that there can be achieved such an advantage thatreduction in the development cost and the step cost can be implemented.

In this case, if the oxidation-preventing insulating layer 12 is formedthicker than the oxygen-barrier metal layers 11 a, the insulatingadhesion layer 13 may be omitted.

Third Embodiment

In the lower electrodes 14 a of the capacitors Q formed in accordancewith the steps shown in the second embodiment, the peeling-off of theIrO layer 14 x from the oxygen-barrier metal layer 11 a rarely occurs.

Therefore, a structure for preventing the peeling-off of the IrO layer14 x from the oxygen-barrier metal layer 11 a without fail in themulti-layered structure, which constitutes the lower electrodes 14 a ofthe capacitors Q, and a method of forming the same will be explainedhereunder.

FIGS. 4A to 4E are sectional views showing steps of manufacturing asemiconductor device according to a third embodiment of the presentinvention.

First, as shown in FIG. 4A, in compliance with the steps shown in thefirst embodiment, the MOS transistors T₁, T₂ are formed on the siliconsubstrate 1 and then the cover layer 7, the first interlayer insulatinglayer 8, and the first to third conductive plugs 10 a to 10 c areformed. Then, in compliance with the steps shown in the secondembodiment, the oxygen-barrier metal layers 11 a each having the samesize as the lower electrode of the capacitor Q are formed on the firstto third conductive plugs 10 a to 10 c and their peripheral areas. Theoxygen-barrier metal layer 11 a is the iridium layer having a thicknessof 400 nm, for example. Then, the oxidation-preventing insulating layer12 and the insulating adhesion layer 13 are formed in sequence on thefirst conductive plug 10 a, the oxygen-barrier metal layers 11 a, andthe first interlayer insulating layer 8. Then, the oxidation-preventinginsulating layer 12 and the insulating adhesion layer 13 are polished bythe CMP method to expose the upper surface of the oxygen-barrier metallayers 11 a.

Then, as shown in FIG. 4B, a conductive adhesion layer 35 is formed onthe oxygen-barrier metal layers 11 a, the oxidation-preventinginsulating layer 12, and the insulating adhesion layer 13. As theconductive adhesion layer 35, an iridium layer of 10 to 50 nm thickness,for example 30 nm, is formed by the sputter.

In this case, the insulating adhesion layer 13 is annealed to preventthe peeling-off of the layer, for example, before or after theconductive adhesion layer 35 is formed. As the annealing method, the RTAexecuted at 750° C. for 60 seconds in the argon atmosphere, for example,may be employed.

Then, as shown in FIG. 4C, the IrO₂ layer 14 x of 30 nm thickness, thePtO layer 14 y of 30 nm thickness, and the Pt layer 14 z of 50 nmthickness, for example, are formed in sequence as the first conductivelayer 14 b on the conductive adhesion layer 35 by the sputter.

Then, the PZT layer of 180 nm thickness, for example, is formed as theferroelectric layer 15 on the first conductive layer 14 b by the sputtermethod or other method. Then, the ferroelectric layer 15 is annealed inthe oxygen-containing atmosphere under the same conditions as the secondembodiment to crystallize. Then, the IrO₂ of 200 nm thickness, forexample, is formed as the second conductive layer 16 on theferroelectric layer 15 by the sputter method.

Then, the hard masks 17 are formed on the second conductive layer 16under the same conditions as the second embodiment.

Then, the second conductive layer 16, the ferroelectric layer 15, thefirst conductive layer 14 b, and the conductive adhesion layer 35 in theregion that is not covered with the hard masks 17 are etchedsequentially. In this case, respective layers from the first conductivelayer 14 b to the conductive adhesion layer 35 are etched by the sputterreaction in the atmosphere containing the halogen element. Therefore,since the oxidation-preventing insulating layer 12 functions as theetching stopper even after the insulating adhesion layer 13 is etched bysuch etching, the first conductive plug is never exposed.

The hard masks 17 are removed after the patterns of the capacitors Q areformed.

With the above, as shown in FIG. 4D, the capacitors Q are formed on thefirst interlayer insulating layer 8. The lower electrode 14 a of thecapacitor Q is made of the first conductive layer 14 b, the conductiveadhesion layer 35, and the oxygen-barrier metal layers 11 a. Also, thedielectric layer 15 a of the capacitor Q is made of the ferroelectriclayer 15. Also, the upper electrode 16 a of the capacitor Q is made ofthe second conductive layer 16.

Then, in order to recover the damage of the ferroelectric layer 15caused by the etching, the recovery annealing of the capacitors Q isexecuted. The recovery annealing in this case is carried out at thesubstrate temperature of 650° C. for 60 minutes in the furnacecontaining the oxygen, for example.

Then, as shown in FIG. 4E, in compliance with the same steps as thesecond embodiment, the capacitor protection layer 18, the secondinterlayer insulating layer 19, the fourth conductive plug 21, theconductive pad 24 a, the first-layer metal wirings 24 b, 24 c, the thirdinterlayer insulating layer 25, the fifth conductive plug 26, the bitline 27, etc. are formed. In this case, in FIG. 4E, the same referencesymbols as those in FIG. 3I denote the same elements.

In the present embodiment described above, the upper surface of theoxygen-barrier metal layers 11 a having the shape of the capacitorslower electrode is exposed by polishing the oxidation-preventinginsulating layer 12 and the insulating adhesion layer 13, then theconductive adhesion layer 35 is formed on the oxygen-barrier metallayers 11 a, the oxidation-preventing insulating layer 12, and theinsulating adhesion layer 13, and then the first conductive layer 14 b,the ferroelectric layer 15, and the second conductive layer 16 areformed sequentially on the conductive adhesion layer 35.

According to this, as shown in FIG. 4B, since the conductive adhesionlayer 35 is interposed between the polished surface of theoxygen-barrier metal layers 11 a and the first conductive layer 14 b,the IrO₂ layer 14 x constituting the first conductive layer 14 b isprevented from peeling off from the oxygen-barrier metal layers 11 a.Such prevention of the peeling-off has been checked based on theexperiment.

It may be considered that, when the oxidation-preventing insulatinglayer 12 and the insulating adhesion layer 13 are polished, the surfaceof the oxygen-barrier metal layers 11 a is altered in quality. If theconductive adhesion layer 35 is not formed, the oxygen-barrier metallayers 11 a and the IrO₂ layer 14 x are put in the state that they areeasily peeled off because they are patterned into the almost same planarshape respectively.

In contrast, in the state of which the conductive adhesion layer 35 madeof the same material as the oxygen-barrier metal layers 11 a is formedon the oxygen-barrier metal layers 11 a, such conductive adhesion layer35 is formed to have good adhesiveness to the oxygen-barrier metallayers 11 a and also the adhesiveness of the conductive adhesion layer35, whose surface is not altered in quality, to the IrO₂ layer 14 x isimproved.

Therefore, according to the present embodiment, if the oxygen-barriermetal layers 11 a is formed in the same size as the lower electrodes 14a of the capacitor Q, the lower electrodes 14 a is never lifted upbecause of the peeling-off.

In this case, in the above embodiment, the conductive adhesion layer 35is made of the same material as the oxygen-barrier metal layers 11 a.But such conductive adhesion layer may be formed of other conductivematerial that has good adhesiveness to the oxygen-barrier metal layers11 a.

Fourth Embodiment

In the first and second embodiments, there is employed such a structurethat the oxygen-barrier metal layers 11 or 11 a is formed on the secondor third conductive plug 10 b, 10 c formed directly under the capacitorsQ and the oxidation-preventing insulating layer 12 is formed on thefirst conductive plug 10 a.

In the present embodiment, to form the oxygen-barrier metal layer on notonly the second and third conductive plugs 10 b, 10 c, which are formeddirectly under the capacitors Q, but also the first conductive plug 10a, which is not formed directly under the capacitors Q, will beexplained hereunder.

FIGS. 5A to 5G are sectional views showing steps of manufacturing asemiconductor device according to a fourth embodiment of the presentinvention.

First, steps required until a structure shown in FIG. 5A is formed willbe explained hereunder.

Like the case shown in FIG. 3A, in compliance with the steps shown inthe second embodiment, the MOS transistors T₁, T₂ are formed on thesilicon substrate 1 and then the cover layer 7, the first interlayerinsulating layer 8, and the first to third conductive plugs 10 a to 10 care formed.

Then, as shown in FIG. 3B, the iridium layer of 400 nm thickness isformed as the conductive oxygen-barrier metal layer 11 a on the first tothird conductive plugs 10 a to 10 c and the first interlayer insulatinglayer 8 by the sputter. The oxygen-barrier metal layer 11 a constitutesa part of the lower electrode of the capacitor Q, as described later.

Then, the masks (not shown) are formed on the oxygen-barrier metal layer11 a over the first, second and third conductive plugs 10 a, 10 b, 10 cand their peripheral areas respectively. It is preferable that, like thesecond embodiment, the hard mask should be employed as the mask.

Then, the oxygen-barrier metal layer 11 a is left on the first, second,and third conductive plugs 10 a, 10 b, 10 c and their peripheral areasrespectively by etching the region of the oxygen-barrier metal layer 11a, which is not covered with the masks. Here, the oxygen-barrier metallayer 11 a left on the second and third conductive plugs 10 b, 10 c ispatterned into a size that is prevent the oxidation of the second andthird conductive plugs 10 b, 10 c and act as the lower electrodes of thecapacitors. Also, the oxygen-barrier metal layer 11 a left on the firstconductive plug 10 a is patterned into an island-like shape that isprevent the oxidation of the first conductive plug 10 a.

Then, as shown in FIG. 5B, the silicon oxide (SiO₂) layer of 300 nmthickness, for example, is formed as the insulating adhesion layer 13 onthe oxygen-barrier metal layer 11 a and the first interlayer insulatinglayer 8 by the CVD method using TEOS, for example. In this case, likethe second embodiment, the oxidation-preventing insulating layer 12 maybe formed under the insulating adhesion layer 13.

Then, as shown in FIG. 5C, the upper surface of the oxygen-barrier metallayer 11 a is exposed by polishing the insulating adhesion layer 13 bymeans of the CMP method while causing the island-like oxygen-barriermetal layer 11 a to function as the stopper layer. In this case, uppersurfaces of the oxygen-barrier metal layer 11 a and the insulatingadhesion layer 13 are made flat by the CMP method.

Then, as shown in FIG. 5D, the IrO₂ layer 14 x of 30 nm thickness, thePtO layer 14 y of 30 nm thickness, and the Pt layer 14 z of 50 nmthickness, for example, are formed in sequence as the first conductivelayer 14 b on the oxygen-barrier metal layer 11 a and the insulatingadhesion layer 13 by the sputter.

In this case, the insulating adhesion layer 13 is annealed to preventthe peeling-off of the layer, for example, before or after the firstconductive layer 14 b is formed. As the annealing method, the RTAexecuted at 750° C. for 60 seconds in the argon atmosphere, for example,may be employed.

Then, the PZT layer of 200 nm thickness, for example, is formed as theferroelectric layer 15 on the first conductive layer 14 b by the similarmethod to that in the second embodiment. Then, the ferroelectric layer15 annealed in the oxygen-containing atmosphere to crystallize. As suchannealing, two-step RTA process having the first step that is executedat the substrate temperature of 600° C. for 90 seconds in the mixed-gasatmosphere consisting of Ar and O₂ and the second step that is executedat the substrate temperature of 750° C. for 60 seconds in the oxygenatmosphere, for example, is employed.

Then, the IrO₂ of 200 nm thickness, for example, is formed as the secondconductive layer 16 on the ferroelectric layer 15 by the sputter method.

Then, the hard masks 17 having the same structure as the secondembodiment are formed on the second conductive layer 16. The hard masks17 are patterned into the planar shape, which is almost same as theoxygen-barrier metal layers 11 a, over the second and third conductiveplugs 10 b, 10 c by the photolithography method. The hard mask 17 has adouble-layered structure consisting of titanium nitride and siliconoxide, for example.

Then, like the second embodiment, the second conductive layer 16, theferroelectric layer 15, and the first conductive layer 14 b in theregion that is not covered with the hard masks 17 are etchedsequentially. Then, the hard masks 17 are removed.

According to the above, as shown in FIG. 5E, the capacitors Q are formedon the first interlayer insulating layer 8. The lower electrode 14 a ofthe capacitor Q is made of the first conductive layer 14 b and theoxygen-barrier metal layers 11 a. Also, the dielectric layer 15 a of thecapacitor Q is made of the ferroelectric layer 15. Also, the upperelectrode 16 a of the capacitor Q is made of the second conductive layer16.

Two capacitors Q are arranged over one well 1 a. These lower electrodes14 a are connected electrically to the second or third n-type impuritydiffusion region 5 b, 5 c via the second or third conductive plug 10 b,10 c respectively.

In this case, since the layer thickness of the first conductive layer 14b to be etched is thin rather than the first conductive layer 14 in thefirst embodiment, the hard masks 17 can also be formed thinner than thefirst embodiment.

Then, in order to recover the damage of the ferroelectric layer 15caused by the etching, the recovery annealing is executed. The recoveryannealing in this case is carried out at the substrate temperature of650° C. for 60 minutes in the furnace containing the oxygen, forexample.

In this manner, when the annealing process such as the recoveryannealing or the like is applied immediately after the patterning of theferroelectric layer 15 is executed, the thermal resistance of the secondand third conductive plugs 10 b, 10 c formed directly under the lowerelectrodes 14 a and the oxidation resistance of the first conductiveplug 10 a not positioned directly under the lower electrodes 14 a aredecided by the oxygen permeability of the oxygen-barrier metal layers 11a respectively.

Although the above thermal processes are required to form the capacitorsQ, the abnormal oxidization is not caused in the first to thirdconductive plugs 10 a to 10 c by the oxygen annealing in the conditionof which the iridium layer of 400 nm, for example, is present as theoxygen-barrier metal layers 11 a on the first to third conductive plugs10 a to 10 c, which are made of tungsten, and their peripheral areasrespectively.

Then, as shown in FIG. 5F, the alumina of 50 nm thickness is formed asthe capacitor protection layer 18 on the capacitors Q and the insulatingadhesion layer 13 by the sputter. This capacitor protection layer 18protects the capacitors Q from the process damage, and may be formed ofPZT in addition to the alumina. Then, the capacitors Q are annealed at650° C. for 60 minutes in the oxygen atmosphere in the furnace.

Then, as shown in FIG. 5G, the fourth conductive plug 21, the conductivepad 24 a, the first-layer metal wirings 24 b, 24 c, the third interlayerinsulating layer 25, the fifth conductive plug 26, the bit line 27, etc.are formed.

In this case, the fourth conductive plug 21 is formed in the secondinterlayer insulating layer 19 and the capacitor protection layer 18over the first n-type impurity diffusion region 5 a, and is connected tothe island-like oxygen-barrier metal layer 11 a. Hence, the bit line 27is connected electrically to the first n-type impurity diffusion region5 a via the fifth conductive plug 26, the conductive pad 24 a, thefourth conductive plug 21, the oxygen-barrier metal layer 11 a, and thefirst conductive plug 10 a.

As described above, in the present embodiment, the island-likeoxygen-barrier metal layer 11 a is formed previously on the first tothird conductive plugs 10 a to 10 c, then the insulating adhesion layer13 is formed on oxygen-barrier metal layers 11 a and the firstinterlayer insulating layer 8, then the oxygen-barrier metal layer 11 ais exposed by polishing the insulating adhesion layer 13 by virtue ofthe CMP method, and then upper portions of the lower electrodes 14 a areformed on the oxygen-barrier metal layers 11 a that covers the secondand third conductive plugs 10 b, 10 c. Here, in the present embodiment,like the second embodiment, the iridium layer is also formed as theoxygen-barrier metal layer.

Accordingly, in the present embodiment, the oxygen-barrier metal layers11 a is formed to use as not only the layer for preventing the abnormaloxidation of the second and third conductive plugs 10 b, 10 c but also apart of the lower electrodes 14 a. Thus, such a merit is achieved thatsteps of forming the layers of the capacitors Q and steps of patterningthem are reduced rather than first embodiment.

In addition, since the oxygen-barrier metal layer 11 a is left like theisland to cover the first conductive plug 10 a to which the bit line isconnected electrically, steps of forming the oxidation-preventinginsulating layer, shown in the first and second embodiments, can beomitted.

As a result, in the crystallization annealing of the ferroelectric layer15 and in the recovery annealing after the capacitors Q are formed, theabnormal oxidation of the first to third conductive plugs 10 a to 10 cis prevented by the oxygen-barrier metal layer 11 a.

In addition, since the upper surfaces of the oxygen-barrier metal layers11 a and the insulating adhesion layer 13 are planarized by the CMPmethod, the first conductive layer 14 a formed on the oxygen-barriermetal layers 11 a and the insulating adhesion layer 13 is made flat inthe neighborhood of the oxygen-barrier metal layers 11 a. Thus,degradation of the crystal of the ferroelectric layer 15 formed on thefirst conductive layer 14 a is prevented.

Also, the conductive plugs 10 a, 21 for the bit-line contact are formedseparately in the first interlayer insulating layer 8 and the secondinterlayer insulating layer 19. As a result, not only the yield of theFeRAM product can be increased but also the existing equipment can bestill employed, so that there can be achieved such a merit thatreduction in the development cost and the step cost can be implemented.

Here, the oxygen-barrier metal layer 11 a constitutes the lowerelectrode 14 a of the capacitor Q. The oxygen-barrier metal layer 11 amay be formed like the island that is narrower than the lower electrode14 a of the capacitor Q, like the first embodiment. In this case, thefirst conductive layer 14 having the quadruple-layered structureemployed in the first embodiment may be formed on the oxygen-barriermetal layer 11 a and the insulating adhesion layer 13 over the secondand third conductive plugs 10 b, 10 c, and then the lower electrodes 14a may be formed by patterning the first conductive layer 14.

In this case, as shown in FIG. 6, like the third embodiment, by adoptingthe conductive adhesion layer 35 formed between the oxygen-barrier metallayer 11 a and the IrO₂ layer 14 x in the lower electrode 14 a of thecapacitor Q, the peeling-off in the lower electrode 14 a is prevented.In this case, the conductive adhesion layer 35 on the island-likeoxygen-barrier metal layer 11 a that covers the first conductive plug 10a is removed by the etching.

Fifth Embodiment

In the above embodiments, the glue layer 9 a and the tungsten layer 9 bare removed from the upper surface of the first interlayer insulatinglayer 8 by the CMP process at the time of forming the first to thirdconductive plugs 10 a to 10 c. It is possible that the erosion and therecess are generated around the first to third contact holes 8 a to 8 cin the CMP process. Since the object of the CMP process in this case isthe glue layer 9 a and the tungsten layer 9 b, upper surfaces of thefirst to third conductive plugs 10 a to 10 c are polished excessivelydue to generation of the erosion and the recess around the contact holes8 a to 8 c. Thus, it is possible that the concave portions are formed inthe first to third conductive plugs 10 a to 10 c and their peripheralareas. There is such a possibility that concave portions are alsogenerated slightly on upper surfaces of the oxygen-barrier metal layers11, 11 a that are formed on the second and third conductive plugs 10 b,10 c in the situation that such concave portions are formed

In the above embodiments, the oxygen-barrier metal layers 11, 11 a areplanarized by the steps of polishing the insulating adhesion layer 13 bymeans of the CMP. But such planarization is still insufficient in somecases.

If the concave portions are present on the oxygen-barrier metal layers11, 11 a, such concave portions affect the lower electrode 14 a, theferroelectric layer 15 a, and the upper electrode 16 a to deteriorateand also it is a chance to make the polarization characteristic of thecapacitor worse.

Therefore, in the present embodiment, a structure of capable ofplanarizing the oxygen-barrier metal layer much more and a method offorming the same will be explained hereunder.

FIGS. 7A to 7I are sectional views showing steps of manufacturing asemiconductor device according to a fifth embodiment of the presentinvention.

First, as shown in FIG. 7A, in compliance with the steps shown in thefirst embodiment, the MOS transistors T₁, T₂ are formed on the siliconsubstrate 1 and then the cover layer 7, the first interlayer insulatinglayer 8, and the first to third conductive plugs 10 a to 10 c areformed.

Then, as shown in FIG. 7B, a conductive oxygen-barrier metal layer 31 isformed on the first to third conductive plugs 10 a to 10 c and the firstinterlayer insulating layer 8 by the sputter.

In the present embodiment, the oxygen-barrier metal layer 31 has adouble-layered structure consisting of a lower metal layer 31 a and anupper metal layer 31 b. The conductive material that can be easilyplanarized by the CMP is selected as the upper metal layer 31 b. Forinstance, the lower metal layer 31 a made of iridium (Ir) and the uppermetal layer 31 b made of iridium oxide (IrO₂) are formed as theoxygen-barrier metal layer 31. The iridium layer is formed in the argonatmosphere by the sputter using an iridium target. Also, the iridiumoxide layer is formed in the atmosphere containing argon and oxygen bythe sputter using the iridium target. Here, the argon gas and the oxygengas are introduced at a ration of 80 and 20 respectively.

The oxygen-barrier metal layer 31 is formed to have the thickness enoughto prevent the abnormal oxidation of the second and third conductiveplugs 10 b, 10 c. In order to prevent the abnormal oxidation of thesecond and third conductive plugs 10 b, 10 c in the annealing at thesubstrate temperature of 550° C. in the oxygen-containing atmosphere,the lower Ir layer 31 a is formed to have a thickness of 200 nm and theupper IrO₂ layer 31 b is formed to have a thickness of 200 nm, forexample.

In this case, in the present embodiment, a concept of the“oxygen-barrier metal” contains metal oxide.

Then, as shown in FIG. 7C, the oxygen-barrier metal layer 31 is left onthe second and third conductive plugs 10 b, 10 c and their peripheralareas by etching the oxygen-barrier metal layer 31 while using a mask(not shown). In this case, it is preferable to use the hard mask as themask, but the resist mask may be employed.

Then, as shown in FIG. 7D, the SiON layer or the Si₃N₄ layer of 100 nmthickness, for example, is formed as the oxidation-preventing insulatinglayer 12 on the oxygen-barrier metal layer 31 and the first interlayerinsulating layer 8 by the CVD method. Then, the SiO₂ layer of 300 nmthickness, for example, is formed as the insulating adhesion layer 13 onthe oxidation-preventing insulating layer 12 by the CVD method usingTEOS, for example.

Then, as shown in FIG. 7E, an upper surface of the upper layer 31 b ofthe oxygen-barrier metal layer 31 is exposed by polishing the insulatingadhesion layer 13 and the oxidation-preventing insulating layer 12 byvirtue of the CMP process. The upper layer 31 b is scraped up to athickness of about 100 nm by executing the CMP process continuously.

Hence, successive upper surfaces of the oxygen-barrier metal layer 31,the insulating adhesion layer 13, and the oxidation-preventinginsulating layer 12 are planarized by the CMP method. In this case, asthe CMP slurry for the silicon oxide, the silicon nitride, and thesilicon nitride oxide, the slurry prepared by adding the water to SS-25manufactured by CABOT Inc., for example, is employed. According to this,the IrO₂ layer constituting the upper layer 31 b is planarized moreeasily than the Ir layer, and is employed as the sacrifice layer.

Then, as shown in FIG. 7F, the Ir layer 14 w of 200 nm thickness, theIrO₂ layer 14 x of 30 nm thickness, the PtO layer 14 y of 30 nmthickness, and the Pt layer 14 z of 50 nm thickness, for example, areformed in sequence as the first conductive layer 14 on the upper layer31 b of the oxygen-barrier metal layer 31, the oxidation-preventinginsulating layer 12, and the insulating adhesion layer 13 by thesputter.

In this case, the insulating adhesion layer 13 is annealed to preventthe peeling-off of the layer, for example, before or after the firstconductive layer 14 is formed. As the annealing method, the RTA executedat 750° C. for 60 seconds in the argon atmosphere, for example, may beemployed.

Then, the PZT layer of 200 nm thickness, for example, is formed as theferroelectric layer 15 on the first conductive layer 14 by the sputtermethod. As the method of forming the ferroelectric layer 15, there arethe MOD method, the MOCVD method, the sol-gel method, etc. in additionto this. Also, as the material of the ferroelectric layer 15, other PZTmaterial such as PLCSZT, PLZT, etc., the Bi-layered structure compoundmaterial such as SrBi₂Ta₂O₉, SrBi₂(Ta,Nb)₂O₉, etc., and other metaloxide ferroelectric substance may be employed in addition to PZT.

Then, the ferroelectric layer 15 is annealed in the oxygen-containingatmosphere to crystallize. As such annealing, two-step RTA processhaving the first step that is executed at the substrate temperature of600° C. for 90 seconds in the mixed-gas atmosphere consisting of Ar andO₂ and the second step that is executed at the substrate temperature of750° C. for 60 seconds in the oxygen atmosphere, for example, isemployed.

Then, the IrO₂ of 200 nm thickness, for example, is formed as the secondconductive layer 16 on the ferroelectric layer 15 by the sputter method.

Then, the TiN layer and the SiO₂ layer are formed in sequence as thehard mask 17 on the second conductive layer 16. The TiN layer is formedby the sputter, and the SiO₂ layer is formed by the CVD method usingTEOS. The hard masks 17 are patterned into the planar shape of thecapacitor over the second and third conductive plugs 10 b, 10 c by thephotography method.

Then, the second conductive layer 16, the ferroelectric layer 15, andthe first conductive layer 14 in the region that is not covered with thehard masks 17 are etched sequentially. In this case, the ferroelectriclayer 15 is etched by the sputter reaction in the atmosphere containingthe halogen element. Here, since the oxidation-preventing insulatinglayer 12 functions as the etching stopper even after the insulatingadhesion layer 13 is etched by such etching, the first conductive plugis never exposed.

According to the above, as shown in FIG. 7G, the capacitors Q are formedon the first interlayer insulating layer 8. The lower electrode 14 a ofthe capacitor Q is made of the first conductive layer 14. Also, thedielectric layer 15 a of the capacitor Q is made of the ferroelectriclayer 15. Also, the upper electrode 16 a of the capacitor Q is made ofthe second conductive layer 16.

Two capacitors Q are arranged over one well 1 a. These lower electrodes14 a are connected electrically to the second or third n-type impuritydiffusion region 5 b, 5 c via the second or third conductive plug 10 b,10 c respectively.

The hard masks 17 are removed after the patterns of the capacitors Q areformed.

Then, in order to recover the damage of the ferroelectric layer 15caused by the etching, the recovery annealing of the capacitors Q iscarried out. The recovery annealing in this case is carried out at thesubstrate temperature of 650° C. for 60 minutes in the furnacecontaining the oxygen, for example.

In this manner, when the annealing process such as the recoveryannealing or the like is applied immediately after the patterning of theferroelectric layer 15 is executed, the thermal resistance of the secondand third conductive plugs 10 b, 10 c formed directly under the lowerelectrodes 14 a is decided by the oxygen permeability of theoxygen-barrier metal layers 31, and also the oxidation resistance of thefirst conductive plug 10 a not positioned directly under the lowerelectrodes 14 a is decided by the oxygen permeability of the insulatingadhesion layer 13 and the oxidation-preventing insulating layer 12.

Although the above thermal processes are required to form the capacitorsQ, the first conductive plug 10 a made of tungsten is not abnormallyoxidized in the condition of which the thickness of the silicon nitridelayer used as the insulating adhesion layer 13 is set to 70 nm.

Also, in the condition of which the iridium layer of 400 nm thickness ispresent on the second and third conductive plugs 10 b, 10 c made oftungsten, the second and third conductive plugs 10 b, 10 c are notabnormally oxidized by the oxygen annealing.

In the present embodiment, a total thickness of the iridium layer is 400nm under the ferroelectric layer 15 and also the IrO₂ layer stillremains about 100 nm in thick. In this case, since both layers preventsthe permeation of oxygen, the abnormal oxidation of the conductive plugs10 b, 10 c is not caused.

Then, as shown in FIG. 7H, the alumina of 50 nm thickness is formed asthe capacitor protection layer 18 on the capacitors Q, theoxidation-preventing insulating layer 12, and the insulating adhesionlayer 13 by the sputter. This capacitor protection layer 18 protects thecapacitors Q from the process damage, and may be formed of PZT inaddition to the alumina. In turn, the capacitors Q are annealed at 650°C. for 60 minutes in the oxygen atmosphere.

Then, as shown in FIG. 7I, in compliance with the steps shown in thefirst embodiment, the fourth conductive plug 21, the conductive pad 24a, the first-layer metal wirings 24 b, 24 c, the third interlayerinsulating layer 25, the fifth conductive plug 26, the bit line 27, etc.are formed.

As described above, in the present embodiment, the oxygen-barrier metallayer 31 having the double-layered structure is left like the island onthe second and third conductive plugs 10 b, 10 c, then theoxidation-preventing insulating layer 12 and the insulating adhesionlayer 13 are formed on the oxygen-barrier metal layer 31 and the firstinterlayer insulating layer 8, then the upper surface of theoxygen-barrier metal layer 31 is exposed by polishing theoxidation-preventing insulating layer 12 and the insulating adhesionlayer 13 by virtue of the CMP process, and then the upper layer 31 b ofthe oxygen-barrier metal layer 31 is reduced in thickness by executingfurther the CMP process.

Since the upper layer 31 b of the oxygen-barrier metal layer 31 isplanarized more easily by the CMP than the Ir layer, it can befacilitated to eliminate the recess on the upper surface of the upperlayer 31 b caused by the concave portion generated on the second andthird conductive plugs 10 b, 10 c and their peripheral areas.

Therefore, since layers of the first conductive layer 14 and theferroelectric layer 15 formed on the upper layer 31 b can be formedflat, deterioration of the layer quality of the ferroelectric layer 15resulted from unevenness can be prevented. As a result, thecharacteristics of the capacitors Q formed by patterning the firstconductive layer 14, the ferroelectric layer 15, and the secondconductive layer 16 can be improved.

Also, the second and third conductive plugs 10 b, 10 c below the lowerelectrodes 14 a constituting the capacitors Q are covered with theoxygen-barrier metal layer 31 and the first conductive plug 10 a,connected to the bit line 27, and the first interlayer insulating layer8 are covered with the oxidation-preventing insulating layer 12. Hence,in the crystallization annealing or the recovery annealing of theferroelectric layer 15, the abnormal oxidation of the first conductiveplug 10 a is prevented by the oxidation-preventing insulating layer 12and also the abnormal oxidation of the second and third conductive plugs10 b, 10 c is prevented by the oxygen-barrier metal layer 31. Inaddition, the oxidation-preventing insulating layer 12 still covers thefirst conductive plug 10 a until the fourth contact hole 19 a is formed,the first conductive plug 10 a is never oxidized by the annealingapplied in the formation of the capacitors Q and subsequent steps.

Further, patterned side surfaces of the oxygen-barrier metal layer 31are covered with the oxidation-preventing insulating layer 12.Therefore, if a size of the oxygen-barrier metal layer 31 is formedalmost equal to the second and third conductive plugs 10 b, 10 c, theoxygen is prevented from entering into the oxygen-barrier metal layer 31from their side surfaces and thus the abnormal oxidation of the secondand third conductive plugs 10 b, 10 c is not generated.

Also, in the present embodiment, the via-to-via contact is formedbetween the first n-type impurity diffusion region 5 a and the contactpad 24 a via two conductive plugs 21, 10 a. As a result, not only theyield of the FeRAM product can be increased but also the existingequipment can be still employed, so that there can be achieved such anadvantage that reduction in the development cost and the step cost canbe implemented.

In this case, like the oxygen-barrier metal layer 14 a in the second andthird embodiments, the oxygen-barrier metal layer 31 having the abovestructure may be shaped into the planar shape, which has the same sizeas the lower electrode 14 a of the capacitor Q, so as to constitute apart of the lower electrode. Also, like the oxygen-barrier metal layers11 a in the fourth embodiment, the oxygen-barrier metal layer 31 havingthe above structure may be left like the island on the first conductiveplug 10 a.

Sixth Embodiment

In the first to fifth embodiments, in order to prevent the oxidation ofthe second and third conductive plugs 10 b, 10 c, the iridium layer isformed as the oxygen-barrier metal layer 11 or 11 a on the second andthird conductive plugs 10 b, 10 c.

The iridium layer is formed on the first interlayer insulating layer 8,which is formed by using TEOS, around the second and third conductiveplugs 10 b, 10 c.

By the way, a plurality of semiconductor devices are formed via ascribing region on one sheet of silicon wafer. A plurality of alignmentmarks 40 shown in FIG. 8 are formed in the scribing region. When thealignment marks 40 are checked after the capacitors Q are formed inaccordance with the steps shown in the first embodiment, traces 41 suchas swellings are found in a part of the alignment marks 40. In thiscase, the alignment mark 40 shown in FIG. 8 consists of a plurality oflayers constituting the capacitor Q.

Hence, when a cross section of the alignment mark 40, in which theswelling seems to be generated, is watched by SEM, a clearance is formedbetween the oxygen-barrier metal layer 11, which is made of iridium, andthe first interlayer insulating layer 8, as shown in FIG. 9.

Accordingly, in the memory cell region of the semiconductor device,adherence between the oxygen-barrier metal layer 11 and the firstinterlayer insulating layer 8 must be enhanced much more. In this case,adherence between the second and third conductive plugs 10 b, 10 c andthe oxygen-barrier metal layer 11 is good.

Therefore, in the present embodiment, a structure for improvingadhesiveness between the oxygen-barrier metal layer 11 and the firstinterlayer insulating layer 8 and steps of forming the same will beexplained hereunder.

FIGS. 10A to 10I are sectional views showing steps of manufacturing asemiconductor device according to a sixth embodiment of the presentinvention.

First, as shown in FIG. 10A, in compliance with the steps shown in thefirst embodiment, the MOS transistors T₁, T₂ are formed on the siliconsubstrate 1, and then the cover layer 7, the first interlayer insulatinglayer 8, and the first to third conductive plugs 10 a to 10 c areformed. In this case, the first interlayer insulating layer 8 is asilicon oxide layer formed by using TEOS as the source gas, for example.

Then, as shown in FIG. 10B, a titanium (Ti) layer having a thickness ofmore than 5 nm but less than 20 nm, for example, 10 nm, is formed as aconductive adhesion layer 37 on the first to third conductive plugs 10 ato 10 c and the first interlayer insulating layer 8 by the sputter. Inthis case, as the conductive adhesion layer 37, a single-layer structureof the titanium nitride (TiN) layer or a double-layered structureconsisting of a TiN upper layer and a Ti lower layer may be employed.

Then, the iridium layer is formed as the conductive oxygen-barrier metallayer 11 on the conductive adhesion layer 37 by the sputter. Asexplained in the first embodiment, the oxygen-barrier metal layer 11 isformed to have a thickness enough to prevent the abnormal oxidation ofthe second and third conductive plugs 10 b, 10 c.

Then, as shown in FIG. 10C, the oxygen-barrier metal layer 11 and theconductive adhesion layer 37 are left like the island on the second andthird conductive plugs 10 b, 10 c and their peripheral areas by etchingthe oxygen-barrier metal layer 11 and the conductive adhesion layer 37while using the same mask (not shown) as the first embodiment. Thus, thefirst conductive plug 10 a is exposed. Then, the masks are removed.

Then, as shown in FIG. 10D, the SiON layer or the Si₃N₄ layer of 100 nmthickness, for example, is formed as the oxidation-preventing insulatinglayer 12 on the oxygen-barrier metal layer 11, the conductive adhesionlayer 37, and the first interlayer insulating layer 8 by the CVD method.Then, the insulating adhesion layer 13 is formed on theoxidation-preventing insulating layer 12. As the insulating adhesionlayer 13, the SiO₂ layer of 100 nm thickness, for example, is formed bythe CVD method using TEOS, for example.

Then, as shown in FIG. 10E, the upper surface of the oxygen-barriermetal layer 11 is exposed by polishing the insulating adhesion layer 13and the oxidation-preventing insulating layer 12 by means of the CMPmethod while causing the oxygen-barrier metal layer 11 to function asthe stopper layer. In this state, since the conductive adhesion layer 37is covered with the oxygen-barrier metal layer 11 and theoxidation-preventing insulating layer 12, the oxidation of theconductive adhesion layer 37 is prevented.

Then, as shown in FIG. 10F, the first conductive layer 14 is formed onthe oxygen-barrier metal layer 11, the oxidation-preventing insulatinglayer 12, and the insulating adhesion layer 13. As shown in the firstembodiment, as the first conductive layer 14, for example, the Ir layer14 w, the IrO₂ layer 14 x, the PtO layer 14 y, and the Pt layer 14 z areformed in sequence by the sputter. In this case, the insulating adhesionlayer 13 is annealed to prevent the peeling-off of the layer, forexample, before or after the first conductive layer 14 is formed.

Then, as shown in the first embodiment, the ferroelectric layer 15 isformed on the first conductive layer 14. Then, the ferroelectric layer15 is crystallized by two-step annealing in the oxygen-containingatmosphere under the same conditions as the first embodiment.

Then, like the first embodiment, the second conductive layer 16 isformed on the ferroelectric layer 15 by the sputter method.

Then, the hard masks 17 each having the planar shape of the capacitorare formed on the second conductive layer 16.

Then, the capacitors Q are formed on the oxygen-barrier metal layer 11,the insulating adhesion layer 13, and the oxidation-preventinginsulating layer 12 by etching in sequence the second conductive layer16, the ferroelectric layer 15, and the first conductive layer 14 in theregion that is not covered with the hard masks 17.

As shown in FIG. 10G, each of the capacitors Q consists of the lowerelectrode 14 a made of the first conductive layer 14, the dielectriclayer 15 a made of the ferroelectric layer 15, and the upper electrode16 a made of the second conductive layer 16. Then, in order to recoverthe damage of the ferroelectric layer 15 caused by the etching, therecovery annealing is carried out.

In this manner, when the annealing process such as the recoveryannealing or the like is applied immediately after the patterning of theferroelectric layer 15 is executed, the thermal resistance of the secondand third conductive plugs 10 b, 10 c formed directly under the lowerelectrodes 14 a is decided by the oxygen permeability of theoxygen-barrier metal layers 11, and the oxidation resistance of thefirst conductive plug 10 a not positioned directly under the lowerelectrodes 14 a is decided by the oxygen permeability of the insulatingadhesion layer 13 and the oxidation-preventing insulating layer 12.

In the annealing process in the above oxygen atmosphere, the conductiveadhesion layer 37 covered with the oxidation-preventing insulating layer12 and the oxygen-barrier metal layers 11 is not oxidized and thusincrease of the resistance of the conductive adhesion layer 37 issuppressed. Also, the oxidation of the first conductive plug 10 a isprevented by the oxidation-preventing insulating layer 12. In addition,the abnormal oxidization of the second and third conductive plugs 10 b,10 c is prevented by the iridium constituting the oxygen-barrier metallayers 11 and the first conductive layer 14.

Then, as shown in FIG. 10H, the capacitor protection layer 18 is formedon the capacitors Q and the insulating adhesion layer 13 by the sputter.Then, the capacitors Q are annealed in the oxygen atmosphere. Then, thesecond interlayer insulating layer 19 is formed on the capacitorprotection layer 18 by the plasma CVD method. Then, the upper surface ofthe second interlayer insulating layer 19 is planarized by the CMPmethod.

Then, as shown in FIG. 10I, in compliance with the same steps as thefirst embodiment, the capacitor protection layer 18, the secondinterlayer insulating layer 19, the fourth conductive plug 21, theconductive pad 24 a, the first-layer metal wirings 24 b, 24 c, the thirdinterlayer insulating layer 25, the fifth conductive plug 26, the bitline 27, etc. are formed. In this case, in FIG. 10I, the same symbols asthose in FIG. 20 denote the same elements.

As described above, according to the present embodiment, since theconductive adhesion layer 37 is formed of the material that has goodadhesiveness to both the oxygen-barrier metal layers 11 and the firstinterlayer insulating layer 8, the clearance is never generated underthe island-like the oxygen-barrier metal layers 11. If the clearance isgenerated under the island-like oxygen-barrier metal layers 11, it ispossible that the second and third conductive plugs 10 b, 10 c areoxidized through the clearance.

In addition, by employing the Ti layer as the conductive adhesion layer37, orientation strength of a (111) face of the oxygen-barrier metallayers 11 is enhanced. Thus, orientation strength of a (111) face of thefirst conductive layer 14 formed on the oxygen-barrier metal layers 11also is enhanced, and also crystallinity of the ferroelectric layer 15formed on the first conductive layer 14 is improved.

Also, when the alignment marks formed on the scribing lines of thesilicon substrate (wafer) 1 were checked, no trace of the swelling wasgenerated and no clearance was found under the iridium layerconstituting the alignment marks.

In the meanwhile, in the above fifth embodiment, in the case of whichthe oxygen-barrier metal layers 31 each having the double-layeredstructure consisting of the Ir lower layer 31 a and the IrO₂ upper layer31 b are formed like the island on the second and third conductive plugs10 b, 10 c and their peripheral areas, this conductive adhesion layer 37may be formed between the oxygen-barrier metal layers 31 and the firstinterlayer insulating layer 8.

More particularly, as shown in FIG. 11, the island-like oxygen-barriermetal layers 31 may be formed on the second and third conductive plugs10 b, 10 c and their peripheral areas via the island-like conductiveadhesion layer 37. Hence, the peeling-off of the oxygen-barrier metallayers 31 formed on the second and third conductive plugs 10 b, 10 c isprevented. In this case, the conductive adhesion layers 37 formed underthe oxygen-barrier metal layers 31 are covered with the oxygen-barriermetal layers 31 and the oxidation-preventing insulating layer 12, theoxidation of the conductive adhesion layers 37 during the annealing toform the capacitors is prevented.

Seventh Embodiment

As shown in the second embodiment, by adopting a size of the island-likeoxygen-barrier metal layers 11 a set equal to the capacitor lowerelectrodes 14 a, the adhesiveness between the oxygen-barrier metallayers 11 a, which is formed to prevent the oxidation of tungstenconstituting the second and third conductive plugs 10 b, 10 c, and thefirst interlayer insulating layer 8 must be improved much more.

FIGS. 12A to 12G are sectional views showing steps of manufacturing asemiconductor device according to a seventh embodiment of the presentinvention.

Next, steps required until a structure shown in FIG. 12A is formed willbe explained hereunder.

First, in compliance with the steps shown in the first embodiment, theMOS transistors T₁, T₂ are formed on the silicon substrate 1, and thenthe cover layer 7, the first interlayer insulating layer 8, and thefirst to third conductive plugs 10 a to 10 c are formed.

Then, the titanium (Ti) layer is formed as the conductive adhesion layer37 on the first to third conductive plugs 10 a to 10 c and the firstinterlayer insulating layer 8 by the sputter. It is preferable that athickness of the titanium layer should be set to keep conductivity ofthe titanium layer if the titanium layer is oxidized, and the thicknessis set to more than 5 nm but less than 20 nm, for example, 10 nm. As theconductive adhesion layer 37, the single-layer structure of the TiNlayer or the double-layered structure consisting of the TiN upper layerand the Ti lower layer may be employed.

Then, the iridium layer of 400 nm thickness is formed as the conductiveoxygen-barrier metal layer 11 a on the conductive adhesion layer 37 bythe sputter. The oxygen-barrier metal layer 11 a constitutes a part ofthe lower electrode of the capacitor Q, as described later.

Then, the hard masks made of titanium nitride, silicon oxide, or thelike are formed as the masks M₂ on the oxygen-barrier metal layer 11 aover the second and third conductive plugs 10 b, 10 c and theirperipheral areas. The planar shape of the masks M₂ are set equal to theshape of the lower electrode of the capacitor, to be described later.

Then, as shown in FIG. 12B, the oxygen-barrier metal layer 11 a and theconductive adhesion layer 37 are etched in the region that is notcovered with the masks M₂. Thus, the oxygen-barrier metal layer 11 a andthe conductive adhesion layer 37 are left on the second and thirdconductive plugs 10 b, 10 c and their peripheral areas to have the sizeof the capacitor. Here, the first conductive plug 10 a is exposed. Then,the masks M₂ are removed.

Then, as shown in FIG. 12C, the oxidation-preventing insulating layer 12and the insulating adhesion layer 13 are formed in sequence on theoxygen-barrier metal layer 11 a, the conductive adhesion layer 37, thefirst conductive plug 10 a, and the first interlayer insulating layer 8under the same conditions as the second embodiment.

Then, as shown in FIG. 12D, the upper surface of the oxygen-barriermetal layer 11 a is exposed by polishing the oxidation-preventinginsulating layer 12 and the insulating adhesion layer 13 by means of theCMP method while causing the oxygen-barrier metal layer 11 a to functionas the stopper layer. Hence, upper surfaces of the oxygen-barrier metallayer 11 a, the insulating adhesion layer 13, and theoxidation-preventing insulating layer 12 are made flat substantially.

Then, as shown in FIG. 12E, like the second embodiment, the IrO₂ layer14 x of 30 nm thickness, the PtO layer 14 y of 30 nm thickness, and thePt layer 14 z of 50 nm thickness, for example, are formed sequentiallyas the first conductive layer 14 b on the oxygen-barrier metal layer 11a, the oxidation-preventing insulating layer 12, and the insulatingadhesion layer 13 by the sputter. In this case, the insulating adhesionlayer 13 is annealed to prevent the peeling-off of the layer before orafter the first conductive layer 14 b is formed.

Then, the ferroelectric layer 15 is formed on the first conductive layer14 under the conditions shown in the second embodiment. Then, theferroelectric layer 15 is annealed in the oxygen-containing atmosphereto crystallize. As shown in the second embodiment, two-step RTA processis employed as such annealing. Then, the IrO₂ layer of 200 nm thickness,for example, is formed as the second conductive layer 16 on theferroelectric layer 15 by the sputter method.

Then, the TiN layer and the SiO₂ layer are formed sequentially on thesecond conductive layer 16, and then the hard masks 17 are formed bypatterning these layers. each having the planar shape of the capacitor.The hard masks 17 are patterned into the capacitor shape, which isalmost similar to the oxygen-barrier metal layer 11 a, over the secondand third conductive plugs 10 b, 10 c.

Then, the second conductive layer 16, the ferroelectric layer 15, andthe first conductive layer 14 b in the region, which is not covered withthe hard masks 17, are etching in sequence under the same conditions asthe second embodiment. Then, the hard masks 17 are removed.

With the above, as shown in FIG. 12F, the capacitors Q are formed on thefirst interlayer insulating layer 8. The lower electrode 14 a of thecapacitor Q is made of the first conductive layer 14 b and theoxygen-barrier metal layer 11 a. Also, the dielectric layer 15 a of thecapacitor Q is made of the ferroelectric layer 15, and the upperelectrode 16 a of the capacitor Q is made of the second conductive layer16.

After this, as shown in FIG. 12G, in compliance with the same steps asthe second embodiment, the capacitor protection layer 18, the secondinterlayer insulating layer 19, the fourth conductive plug 21, theconductive pad 24 a, the first-layer metal wirings 24 b, 24 c, the thirdinterlayer insulating layer 25, the fifth conductive plug 26, the bitline 27, etc. are formed. In this case, in FIG. 12G, the same symbols asthose in FIG. 3I denote the same elements.

As described above, according to the present embodiment, since theconductive adhesion layer 37 is formed of that material that has goodadhesiveness to both the oxygen-barrier metal layers 11 a and the firstinterlayer insulating layer 8, the clearance is never generated underthe oxygen-barrier metal layers 11 a constituting the lower electrode 14a of the capacitor Q. In addition, by adopting the Ti layer as theconductive adhesion layer 37, the orientation strength of the (111) faceof the lower electrode 14 a is enhanced. Thus, the crystallinity of theferroelectric layer 15 is improved.

By the way, as shown in the fourth embodiment, in the structure in whichthe island-like oxygen-barrier metal layer 11 a is formed on not onlythe second and third conductive plugs 10 b, 10 c and their peripheralareas but also the first conductive plug 10 a and its peripheral area,the conductive adhesion layer 37 may be formed between the firstinterlayer insulating layer 8 and the island-like oxygen-barrier metallayers 11 a around the first conductive plug 10 a and its peripheralarea.

Accordingly, as shown in FIG. 13, the clearance is never formed underthe island-like oxygen-barrier metal layers 11 a that are formed on notonly the second and third conductive plugs 10 b, 10 c but also the firstconductive plug 10 a. As a result, the first to third conductive plugs10 a to 10 c are not oxidized in the annealing in the oxygen atmosphere.If the clearance is generated under the island-like oxygen-barrier metallayers 11 a, it is possible that the first to third conductive plugs 10a to 10 c are oxidized through the clearance.

Eighth Embodiment

In the above embodiment, the steps of patterning the oxygen-barriermetal layers 11 or 11 a to leave on the second and third conductiveplugs 10 b, 10 c and their peripheral areas like the island. The hardmasks M₁, M₂ may be employed upon patterning the oxygen-barrier metallayers 11 or 11 a.

In the condition of which titanium nitride is employed as the materialof the hard masks M₁, M₂, it may be considered that, since the hardmasks are formed as the conductive mask, such hard masks are not removedto leave as it is after the patterning of the oxygen-barrier metallayers 11 or 11 a. However, the titanium nitride is oxidized by theoxygen annealing, which is applied to form the capacitor, and thus itsresistance is increased higher. Hence, it is not preferable to leave thetitanium nitride as it is. Therefore, after the oxygen-barrier metallayers 11 or 11 a are patterned, the hard masks M₁, M₂ made of titaniumnitride are removed by the wet etching using ammonium peroxide, forexample.

However, as explained in the first and second embodiments, after theoxygen-barrier metal layers 11 or 11 a are patterned, a part of both thetungsten layer 9 b constituting the first conductive plug 10 a and theglue layer 9 a made of titanium nitride/titanium is exposed from thefirst interlayer insulating layer 8. Therefore, since the titaniumnitride constituting the first conductive plug 10 a is also etchedsimultaneously when the hard masks M₁, M₂ made of titanium nitride areremoved, a recess is generated in the first conductive plug 10 a. Sincethe insulating material is filled in the recess, it is possible toincrease the resistance of the first conductive plug 10 a.

As a result, in the present embodiment, memory cell forming steps ofemploying a new method of removing the hard masks after the patterningof the oxygen-barrier metal layers 11 or 11 a will be explainedhereunder.

FIGS. 14A to 14G are sectional views showing steps of manufacturing asemiconductor device according to an eighth embodiment of the presentinvention.

Next, steps required until a structure shown in FIG. 14A is formed willbe explained hereunder.

First, in compliance with the steps shown in the first embodiment, theMOS transistors T₁, T₂ are formed on the silicon substrate 1, and thenthe cover layer 7, the first interlayer insulating layer 8, and thefirst to third conductive plugs 10 a to 10 c are formed. After this, thefirst interlayer insulating layer 8 is exposed to the nitrogen plasmaatmosphere at the substrate temperature of 350° C. for 120 seconds.

Then, as shown in FIG. 14B, the iridium layer is formed as theconductive oxygen-barrier metal layer 11 on the first to thirdconductive plugs 10 a to 10 c and the first interlayer insulating layer8 by the sputter. The iridium layer is formed to have a thickness of 200nm, for example.

Then, masks M₃ made of titanium nitride are formed on the oxygen-barriermetal layer 11 over the second and third conductive plugs 10 b, 10 c andtheir peripheral areas. A titanium nitride (TiN) layer of 200 nmthickness is formed on the oxygen-barrier metal layer 11 and then isleft as the masks M₃ on the second and third conductive plugs 10 b, 10 cand their peripheral areas by etching the TiN layer while using resistpatterns (not shown). In this case, the TiN layer is etched by usingBCl₃ and Cl₂. Then, the resist patterns are removed.

Then, as shown in FIG. 14C, the oxygen-barrier metal layer 11 is etchedin the region that is not covered with the masks M₃. Thus, theoxygen-barrier metal layer 11 is left like the island on the second andthird conductive plugs 10 b, 10 c and their peripheral areas. The firstconductive plug 10 a is exposed by the etching of the oxygen-barriermetal layer 11.

The etching of the oxygen-barrier metal layer 11 made of iridium isexecuted by using the ICP plasma etching equipment. The electric powerof 800 W is applied to the coil antenna arranged at the upper portion inthe chamber of the ICP plasma etching equipment, and the bias power of700 W is applied to the stage on which the wafer is loaded in thechamber. Also, the pressure in the chamber is set to 0.4 Pa, and thestage temperature is set to 400° C. Also, as the etching gas of theoxygen-barrier metal layer 11, HBr and O₂ are introduced into thechamber at flow rates of 10 sccm and 40 sccm respectively. Also, afterthe etching of the oxygen-barrier metal layer 11 is completed, theover-etching is carried out for a time, a length of which is equal tothe etching time, not to leave the oxygen-barrier metal layer 11 in theregion except the second and third conductive plugs 10 b, 10 c and theirperipheral areas.

Then, as shown in FIG. 14D, the SiON layer or the Si₃N₄ layer of 100 nmthickness, for example, is formed as the oxidation-preventing insulatinglayer 12 on the masks M₃, the oxygen-barrier metal layer 11, the firstinterlayer insulating layer 8, and the first conductive plug 10 a by theCVD method. Then, the insulating adhesion layer 13 is formed on theoxidation-preventing insulating layer 12. As the insulating adhesionlayer 13, the SiO₂ layer of 100 nm thickness is formed by the CVD methodusing TEOS, for example.

Then, as shown in FIG. 14E, the insulating adhesion layer 13, theoxidation-preventing insulating layer 12, and the masks M₁ are polishedby the CMP method while causing the oxygen-barrier metal layer 11 tofunction as the stopper layer. Hence, the masks are removed and an uppersurface of the oxygen-barrier metal layer 11 is exposed. In this case,the upper surfaces of the oxygen-barrier metal layer 11, the insulatingadhesion layer 13, and the oxidation-preventing insulating layer 12 aremade flat substantially.

This CMP method is executed by using the polishing machine. Also, aproduct name IC1010 manufactured by Rodel Nitta Company, for example, isused as the abrasive cloth, and SS-25E manufactured by CabbotCorporation, for example, is used as the slurry. The polishing time is70 second, for example.

Then, as shown in FIG. 14F, in compliance with the steps shown in thefirst embodiment, the capacitors Q are formed on theoxidation-preventing insulating layer 12, and the insulating adhesionlayer 13 on the island-like oxygen-barrier metal layers 11. Thecapacitor Q consists of the lower electrode 14 a, the ferroelectriclayer 15 a, and the upper electrode 16 a. The lower electrode 14 a isconnected to the conductive plug 10 b (10 c) via the island-likeoxygen-barrier metal layer 11.

After this, as shown in FIG. 14G, in compliance with the same steps asthe first embodiment, the capacitor protection layer 18, the secondinterlayer insulating layer 19, the fourth conductive plug 21, theconductive pad 24 a, the first-layer metal wirings 24 b, 24 c, the thirdinterlayer insulating layer 25, the fifth conductive plug 26, the bitline 27, etc. are formed. In this case, in FIG. 14G, the same symbols asthose in FIG. 20 denote the same elements.

As described above, according to the present invention, theoxygen-barrier metal layer 11 is patterned by using the masks M₃ formedover the second and third conductive plugs 10 b, 10 c, then theoxidation-preventing insulating layer 12 and the insulating adhesionlayer 13 are formed on the masks M₃, the first interlayer insulatinglayer 8, and the first conductive plug 10 g without removal of the masksM₃, and then the masks M₃ are removed by the polishing executed when theoxidation-preventing insulating layer 12 and the insulating adhesionlayer 13 are to be polished.

Therefore, TiN constituting the glue layer 9 a of the first conductiveplug 10 a is not etched in removing the masks M₃. As a result, the firstconductive plug 10 a does not suffer damage in removing the masks M₃,and thus the first conductive plug 10 a together with the second andthird conductive plugs 10 b, 10 c connect the impurity diffusion region5 a to the bit line 27 on a via-to-via basis. In addition, theindependent step of removing the masks M₃ only is omitted and thusthroughput is improved.

In the meanwhile, as set forth in Patent Application Publication (KOKAI)Hei 11-126778, if the masks M₃ is removed by the CMP method in the stateshown in FIG. 14C immediately after the oxygen-barrier metal layer 11 ispatterned, the moisture enters into the surface of the first interlayerinsulating layer 8 to cause the first conductive plug 10 a to oxidize.Therefore, such situation is not preferable.

In this case, material of the masks M₃ employed to pattern theoxygen-barrier metal layer 11 is not limited to titanium nitride. Thedouble-layered structure obtained by forming titanium nitride (TiN) andsilicon oxide (SiO₂) sequentially may be employed, or such masks may beformed of other material.

Ninth Embodiment

Like the eighth embodiment, removal of the mask M₂ shown in the secondembodiment may be executed at the same time when the planarization ofthe oxidation-preventing insulating layer 12 and the insulating adhesivelayer 13 is executed by the CMP method after the oxidation-preventinginsulating layer 12 and the insulating adhesive layer 13 are formed onthe mask M₂ and the first interlayer insulating layer 8.

Therefore, steps of forming a hard mask having a double-layeredstructure consisting of a TiN layer and an SiO₂ layer as a mask used topattern an oxygen barrier metal layer 11 a and then removing such hardmask by the CMP method will be explained hereunder.

FIGS. 15A to 15D are sectional views showing steps of manufacturing asemiconductor device according to a ninth embodiment of the presentinvention, which are taken along a I-I line in a plan view of the memorycell region shown in FIG. 17. That is, FIGS. 15A to 15D show steps offorming the island-like oxygen barrier metal layer 11 a under thecapacitor Q, which is formed on one side of one p-type well 1 a, and twocapacitors Q, which are positioned adjacently to each other in theextending direction of the gate electrodes (word lines) 4 a, 4 b,respectively.

Steps required until a structure shown in FIG. 15A is formed will beexplained hereunder.

First, in compliance with the steps shown in the first embodiment, theMOS transistors T₁, T₂ are formed on the silicon substrate 1, and thenthe cover layer 7 for covering the MOS transistors T₁, T₂, the firstinterlayer insulating layer 8, the first to third conductive plugs 10 ato 10 c are formed sequentially. Then, the first interlayer insulatinglayer 8 is exposed to the nitrogen plasma atmosphere at the substratetemperature of 350° C. for 120 sec.

Then, the iridium (Ir) layer is formed as the conductive oxygen barriermetal layer 11 a on the first to third conductive plugs 10 a to 10 c andon the first interlayer insulating layer 8 by the sputter. The Ir layeris formed to have a thickness of 400 nm, for example.

Then, a TiN layer 51 of 200 nm thickness is formed on the oxygen barriermetal layer 10 a by the sputter method. Then, an SiO₂ layer 52 of 1000nm thickness is formed on the TiN layer 51 by the CVD method using TEOS.

Then, a resist is coated on the SiO₂ layer 52, and then resist patterns53 each having an almost capacitor planar shape are formed over thesecond and third conductive plugs 10 b, 10 c and their peripheral areasby exposing/developing the resist. Then, areas of the SiO₂ layer 52 andthe TiN layer 51, which are not covered with the resist pattern 53, areetched. Thus, the SiO₂ layer 52 and the TiN layer 51 being left underthe resist patterns 53 are used as a first hard mask 50.

Then, the resist patterns 53 are removed by the oxygen ashing.

Then, as shown in FIG. 15B, areas of the oxygen barrier metal layer 11a, which are not covered with the first hard mask 50, are etched. Thus,the oxygen barrier metal layer 11 a is left like an island on the secondand third conductive plugs 10 b, 10 c and their peripheral areas. Theoxygen barrier metal layer 11 a is patterned by the dry etching using amixed gas of HBr, O₂, and C₄F₈ while setting the temperature of thestage, on which the silicon substrate 1 is loaded, to 400° C. In thiscase, the SiO₂ layer 52 constituting the first hard mask 50 is alsoetched into an almost cone shape at the time of such etching.

Then, as shown in FIG. 15C, a silicon oxide nitride (SiON) layer or asilicon nitride (Si₃N₄) layer of 350 nm thickness is formed as anoxidation-preventing insulating layer 54 on the first hard mask 50, theoxygen barrier metal layer 11 a, and the first interlayer insulatinglayer 8 by the CVD method. The SiON layer is formed by the CVD methodusing silane, ammonia, and oxygen, for example. Also, the Si₃N₄ layer isformed by the CVD method using silane and ammonia, for example.

Then, an SiO₂ layer of 600 nm thickness is formed as a sacrifice oxidelayer 55 on the oxidation-preventing insulating layer 54 by the CVDmethod using TEOS as the growth gas. In this case, in the presentembodiment, the insulating adhesive layer formed in the aboveembodiments is not formed on the oxidation-preventing insulating layer.

Then, as shown in FIG. 15B, the sacrifice oxide layer 55, theoxidation-preventing insulating layer 54, and the first hard mask 50 arepolished by the CMP method while causing the island-like oxygen barriermetal layer 11 a to act as a stopper layer. Thus, the first hard mask 50is removed and thus an upper surface of the oxygen barrier metal layer11 a is exposed. Then, the oxidation-preventing insulating layer 54 isleft on the first interlayer insulating layer 8 and the first conductiveplug 10 a on the side of the island-like oxygen barrier metal layer 11a. Also, the thin sacrifice oxide layer 55 is left on theoxidation-preventing insulating layer 54. In this case, upper surfacesof the oxygen barrier metal layer 11 a, the oxidation-preventinginsulating layer 54, and the sacrifice oxide layer 55 are madesubstantially flat. The abrasive cloth and the slurry shown in theeighth embodiment are employed at the time of such polishing.

Then, the capacitors are formed by the steps shown in the secondembodiment, but their details will be omitted herein.

As described above, the first hard mask 50 used only for the patterningof the island-like oxygen barrier metal layer 11 a, which is used as apart of the capacitor lower electrode, is removed at the time of theplanarization of the oxidation-preventing insulating layer 54.Therefore, like the eighth embodiment, the isolated step of removingonly the first hard mask 50 is eliminated.

Meanwhile, if an interval between the capacitors, which are arrangedadjacently in the extending direction of the gate electrodes (wordlines) 4 a, 4 b, is narrow such as about 1 μm and the oxygen barriermetal layer 11 a is thick such as about 400 nm, for example, an aspectratio of a space between the island-like oxygen barrier metal layers 11a and the first hard masks 50 becomes large, as shown in FIG. 15C. Thus,the space is not perfectly buried by the oxidation-preventing insulatinglayer 54, and thus a narrow clearance 54 s is generated in theoxidation-preventing insulating layer 54. Since the oxidation-preventinginsulating layer 54 becomes thin under the clearance 54 s, the followingdisadvantage is caused in the later capacitor forming steps.

In this case, if the interval between the capacitors Q shown in FIG. 17is wide, the clearance 54 s shown in FIG. 15C is not generated. Hence,there is caused no trouble to execute both the removal of the first hardmasks 50 having the double-layered structure and the planarization ofthe oxidation-preventing insulating layer 54 simultaneously by the CMPmethod.

Therefore, the capacitor forming steps executed after the first hardmasks 50 is removed will be explained simply hereunder.

First, as shown in FIG. 16A, a first conductive layer 14 b is formed onthe island-like oxygen barrier metal layer 11 a, theoxidation-preventing insulating layer 54, and the sacrifice oxide layer55. As the first conductive layer 14 b, a laminated structure unlike thesecond embodiment is formed. For example, an Ir layer 14 w of 30 nmthickness, an IrO₂ layer 14 x of about 30 nm thickness, a Pt layer 14 vof 15 nm thickness, a PtO layer 14 y of about 25 nm thickness, and a Ptlayer 14 z of about 50 nm thickness are formed sequentially by thesputter.

In this case, the oxidation-preventing insulating layer 54 is annealedin the argon atmosphere to prevent the peeling-off of the layer, forexample, before or after the formation of the first conductive layer 14b.

Then, a ferroelectric layer 15 and a second conductive layer 16 areformed on the first conductive layer 14 b. As the ferroelectric layer15, a PZT layer of 140 to 200 nm thickness is formed by the sputtermethod. Then, the ferroelectric layer 15 is annealed in the oxygenatmosphere to crystallize the ferroelectric layer 15. In this case, asthe growth method and the material of the ferroelectric layer 15, thegrowth method and the material shown in the second embodiment may beemployed in addition to this.

Then, a TiN layer 56 of 200 nm thickness is formed on the secondconductive layer 16 by the PVD method. Then, an SiO₂ layer 57 of 900 nmthickness is formed on the TiN layer 56 by the CVD method using TEOS.

Then, a resist is coated on the SiO₂ layer 57. Then, resist patterns 59each having an almost capacitor planar shape are formed over the secondand third conductive plugs 10 b, 10 c and their peripheral areas byexposing/developing the resist. Then, areas of the SiO₂ layer 57 and theTiN layer 56, which are not covered with the resist pattern 59, areetched. Thus, the SiO₂ layer 57 and the TiN layer 56 being left underthe resist patterns 59 are used as a second hard mask 58. In this case,the SiO₂ layer 57 is etched by using a mixed gas of C₄F₈, Ar, and CF₄.Also, the TiN layer 56 is etched by using a mixed gas of BCl₃ and Cl₂,or other gas.

Then, the resist patterns 59 are removed by the oxygen ashing.

Then, as shown in FIG. 16B, the second conductive layer 16, theferroelectric layer 15, and the first conductive layer 14 b in areasthat are not covered with the second hard mask 58 are etchedsequentially. In this case, all the second conductive layer 16, theferroelectric layer 15, and the first conductive layer 14 b are etchedby using the ICP plasma etching equipment. The substrate temperature atthe time of etching is set to 400° C. Also, a mixed gas consisting ofHBr and O₂ is used as the etching gas for the first conductive layer 14b and the second conductive layer 16. Also, a mixed gas consisting ofCl₂ and Ar is used as the etching gas for the ferroelectric layer 15.

Thus, the capacitors Q connected to the second and third conductiveplugs 10 b, 10 c respectively are formed on the first interlayerinsulating layer 8. The lower electrode 14 a of the capacitor Q isconstructed by the first conductive layer 14 b and the oxygen barriermetal layer 11 a. Also, the dielectric layer 15 a of the capacitor Q isconstructed by the ferroelectric layer 15, and the upper electrode 16 aof the capacitor Q is constructed by the second conductive layer 16.

In this case, the SiO₂ layer 57 constituting the second hard mask 58 isalso etched into an almost cone shape at the time of such etching.

Then, as shown in FIG. 16C, the SiO₂ layer 57 constituting the secondhard mask 58 is removed by the two-frequency reactive ion etching(two-frequency RIE) method using a mixed gas of C₄F₈, Ar, and O₂. At thetime of etching of the SiO₂ layer 57, the oxidation-preventinginsulating layer 54 consisting of the SiON layer and the Si₃N₄ layerfunctions as the etching stopper layer. Then, the TiN layer 56 of thesecond hard mask 58 is removed by the wet etching using a mixed chemicalconsisting of hydrogen peroxide and ammonia.

Then, in order to recover the damage of the ferroelectric layer 15caused by the etching, the recovery annealing of the capacitor Q isexecuted. The recovery annealing in this case is executed at thesubstrate temperature of 650° C. for 60 min in the atmosphere containingthe oxygen, for example.

Then, steps goes to the steps of forming the second interlayerinsulating layer, etc. like the above embodiments, but their detailswill be omitted herein.

By the way, as shown in FIG. 15C, if the interval between the patternseach of which is composed of the island-like oxygen barrier metal layer11 a and the first hard mask 50 becomes narrow, the clearance 54 s isformed in the oxidation-preventing insulating layer 54 formed betweensuch patterns. Thus, as shown in FIG. 16B, a thickness of theoxidation-preventing insulating layer 54 is reduced when the secondconductive layer 16, the ferroelectric layer 15, and the firstconductive layer 14 b are etched, and thus the first interlayerinsulating layer 8 is etched through the clearance 54 s to generate anconcave portion. In addition, a depth of such concave portion isincreased much more through the clearance 54 s when the SiO₂ layer 57 ofthe second hard mask 58 is removed.

If the depth of such concave portion in the first interlayer insulatinglayer 8 is increased, the oxygen enters into the first interlayerinsulating layer 8 from the concave portion during the recoveryannealing executed after the patterning of the capacitors Q, and thenthe oxygen penetrates through the first interlayer insulating layer 8.Thus, the second and third conductive plugs 10 b, 10 c made of tungstenare oxidized, and further the MOS transistors T1, T2 are deteriorated.

On the contrary, it may be thought of that the aspect ration of thespace between the island-like oxygen barrier metal layers 11 a isreduced by thinning the oxygen barrier metal layer 11 a to prevent thegeneration of the clearance 54 s.

However, the selective etching ratio of the SiO₂ layer 52 constitutingthe first hard mask 50 is small such as about 5 to 7 in comparison withthe SiON layer or the Si₃N₄ layer constituting the oxidation-preventinginsulating layer 54 made of SiO₂. Therefore, the oxidation-preventinginsulating layer 54 as well as the first hard mask 50 is etched duringthe etching of the first hard mask 50, and thus a thickness of theoxidation-preventing insulating layer 54 is reduced by about 150 nm. Inaddition, the thickness of the oxidation-preventing insulating layer 54is also reduced by about 100 nm by the overetching that is causedsubsequently to the formation of the capacitors Q. In contrast, in orderto prevent the oxidation of the first conductive plug 10 a by theoxidation-preventing insulating layer 54, the thickness of theoxidation-preventing insulating layer 54 needs about 100 nm with a smallmargin.

Therefore, the thickness of the oxidation-preventing insulating layer 54must be formed thick to leave 350 nm after the polishing of theoxidation-preventing insulating layer 54. If the thickness of theoxidation-preventing insulating layer 54 is set to 350 nm, a thicknessof the oxygen barrier metal layer 11 a must be set to 350 nm or morewith regard to the polishing of the oxidation-preventing insulatinglayer 54 by the CMP method.

In this case, in the first to eighth embodiments, respective thicknessesof the oxidation-preventing insulating layer 12 and the insulatingadhesive layer 13 are given by the values obtained in the condition thatreduction in thicknesses of such layers are seldom considered.

With the above, if the interval between the capacitors Q is narrowedrather than 1 μm, for example, it is not preferable that the removal ofthe first hard mask 50 made of inorganic material and the planarizationof the oxidation-preventing insulating layer 54 should executedsimultaneously.

Therefore, in a next tenth embodiment, a method of removing the firsthard mask 50 not to form the concave portion in the first interlayerinsulating layer 8 between the capacitors Q executed when the intervalbetween the capacitors Q becomes narrower than 1 μm will be explainedhereunder.

Tenth Embodiment

FIGS. 18A to 18G are sectional views showing steps of manufacturing asemiconductor device according to a tenth embodiment of the presentinvention, which are taken along a I-I line in FIG. 17.

Steps required until a structure shown in FIG. 18A is formed will beexplained hereunder.

First, in compliance with the steps shown in the first embodiment, theMOS transistors T₁, T₂ are formed on the silicon substrate 1, and thenthe cover layer 7 for covering the MOS transistors T₁, T₂, the firstinterlayer insulating layer 8, the first to third conductive plugs 10 ato 10 c are formed sequentially. Then, the first interlayer insulatinglayer 8 is exposed to the nitrogen plasma atmosphere at the substratetemperature of 350° C. for 120 sec.

Then, the iridium layer is formed as a conductive oxygen barrier metallayer 11 b on the first to third conductive plugs 10 a to 10 c and onthe first interlayer insulating layer 8 by the sputter. The iridiumlayer is formed to have a thickness of 200 nm, for example.

Then, a TiN layer 60 of 100 nm thickness is formed on the oxygen barriermetal layer 11 b by the sputter method.

Then, a resist is coated on the TiN layer 60, and then resist patterns61 each having an almost capacitor planar shape are formed over thesecond and third conductive plugs 10 b, 10 c and their peripheral areasby exposing/developing the resist. Then, areas of the TiN layer 60,which are not covered with the resist pattern 61, are etched. Thus, theTiN layer 60 being left under the resist patterns 61 are used as a firsthard mask 60 a.

Then, the resist patterns 61 are removed by the oxygen ashing.

Then, as shown in FIG. 18B, areas of the oxygen barrier metal layer 11b, which are not covered with the first hard mask 60 a, are etched.Thus, the oxygen barrier metal layer 11 b is left like an island on thesecond and third conductive plugs 10 b, 10 c and their peripheral areas.The oxygen barrier metal layer 11 b is patterned by the high-temperaturedry etching using a mixed gas of HBr, O₂, and C₄F₈ while setting thesubstrate temperature to 400° C. In this case, the SiO₂ layer 52constituting the first hard mask 50 is also etched into an almost coneshape at the time of such etching.

Then, as shown in FIG. 18C, an alumina layer for covering the first hardmask 60 a and the oxygen barrier metal layer 11 b is formed as anoxidation-preventing insulating layer 62 on the first interlayerinsulating layer 8 to have a thickness of 100 to 150 nm. The aluminalayer may be formed either the sputter method or the CVD method. As thecondition that the alumina layer is formed by the MOCVD method, a gas inwhich hydrogen (H₂) or ozone (O₃) is added to trimethylaluminium(Al(CH₃)₃), for example, is employed, and the substrate temperature isset to 300° C., for example.

Then, an SiO₂ layer of 600 nm thickness is formed as a sacrifice oxidelayer 63 on the oxidation-preventing insulating layer 62. The sacrificeoxide layer 63 is formed by the CVD method using TEOS, for example.

Then, as shown in FIG. 18D, the sacrifice oxide layer 63, theoxidation-preventing insulating layer 62, and the first hard mask 60 aare polished by the CMP method while causing the island-like oxygenbarrier metal layer 11 b to act as the stopper layer. At the time ofsuch polishing, the abrasive cloth and the slurry shown in the eighthembodiment are employed. Thus, upper surfaces of the oxygen barriermetal layer 11 a, the oxidation-preventing insulating layer 54, and thesacrifice oxide layer 55 are made substantially flat, and the first hardmask 60 a is removed and thus an upper surface of the underlying oxygenbarrier metal layer 11 b is exposed. In addition, theoxidation-preventing insulating layer 54 left on the side of theisland-like oxygen barrier metal layer 11 b covers the first interlayerinsulating layer 8 and the first conductive plug 10 a. In this case, thesacrifice oxide layer 63 is left thin on the oxidation-preventinginsulating layer 62.

As described above, if the island-like oxygen barrier metal layer 11 bis used as a part of the capacitor lower electrode, the first hard mask60 a is removed from the upper surface of the island-like oxygen barriermetal layer 11 b by the CMP method subsequently to theoxidation-preventing insulating layer 63. Therefore, like the eighth andninth embodiments, the isolated step of removing only the first hardmask 60 a is eliminated.

Then, as shown in FIG. 18E, the first conductive layer 14 b is formed onthe oxygen barrier metal layer 11 b, the oxidation-preventing insulatinglayer 62, and the sacrifice oxide layer 63. As the first conductivelayer 14 b, the laminated structure unlike the second embodiment isformed. For example, an Ir layer 14 w of 100 to 200 nm thickness, anIrO₂ layer 14 x of about 30 nm thickness, a Pt layer 14 v of 15 nmthickness, a PtO layer 14 y of about 25 nm thickness, and a Pt layer 14z of about 50 nm thickness are formed sequentially.

In this case, the oxidation-preventing insulating layer 54 is annealedin the argon atmosphere to prevent the peeling-off of the layer, forexample, before or after the formation of the first conductive layer 14b.

Then, the ferroelectric layer 15 and the second conductive layer 16 areformed on the first conductive layer 14 b. As the ferroelectric layer15, a PZT layer of 140 to 200 nm thickness is formed by the sputtermethod. Then, the ferroelectric layer 15 is annealed in the oxygenatmosphere to crystallize the ferroelectric layer 15. In this case, asthe growth method and the material of the ferroelectric layer 15, thegrowth method and the material shown in the second embodiment may beemployed in addition to this.

Then, an IrO₂ layer of about 200 to 300 nm thickness, for example, isformed as the second conductive layer 16 on the ferroelectric layer 15by the sputter method.

Then, a TiN layer 56 of 200 nm thickness is formed on the secondconductive layer 16 by the PVD method using TEOS. Then, an SiO₂ layer 57of 900 nm thickness is formed on the TiN layer 56 by the CVD methodusing TEOS.

Then, a resist is coated on the SiO₂ layer 57. Then, resist patterns 59each having an almost capacitor planar shape are formed over the secondand third conductive plugs 10 b, 10 c and their peripheral areas byexposing/developing the resist. Then, areas of the SiO₂ layer 57 and theTiN layer 56, which are not covered with the resist pattern 59, areetched. Thus, the SiO₂ layer 57 and the TiN layer 56 being left underthe resist patterns 59 are used as a second hard mask 58. In this case,the TiN layer 56 is etched by using a mixed gas of BCl₃ and Cl₂, or Cl₂or other gas. Also, the SiO₂ layer 57 is etched by setting the substratetemperature to 0 to 20° C. In this case, the dry etching of the SiO₂layer 57 and the TiN layer 56 is executed by exchanging the etcher.

Then, the resist patterns 59 are removed by the oxygen ashing.

Then, as shown in FIG. 18F, the second conductive layer 16, theferroelectric layer 15, and the first conductive layer 14 b in areasthat are not covered with the second hard mask 58 are etchedsequentially. In this case, all the second conductive layer 16, theferroelectric layer 15, and the first conductive layer 14 b are etchedby using the ICP plasma etching equipment.

As these etching conditions, a pressure in the chamber is set to 0.4 Pa,the wafer stage temperature is set to 400° C., a source power is set to800 watt, and a bias power is set to 700 watt. Also, as the etching gasfor the second conductive layer 16 and the first conductive layer 14 b,HBr and O₂ are supplied to the etching chamber at a flow rate of 10 sccmand 40 sccm respectively. Also, as the etching gas for the ferroelectriclayer 15, Cl₂ and Ar are supplied to the etching chamber at a flow rateof 40 sccm and 10 sccm respectively. In this case, the source power is apower of a high-frequency power supply applied to an antenna of the ICPplasma etching equipment. The bias power is a power of a high-frequencypower supply applied to the semiconductor wafer (silicon substrate) 1.

Thus, a plurality of capacitors Q that are connected to the second andthird conductive plugs 10 b, 10 c separately are formed on the firstinterlayer insulating layer 8. The lower electrode 14 a of the capacitorQ is constructed by the first conductive layer 14 b and the oxygenbarrier metal layer 11 b. Also, the dielectric layer 15 a of thecapacitor Q is constructed by the ferroelectric layer 15, and the upperelectrode 16 a of the capacitor Q is constructed by the secondconductive layer 16.

In this case, at the time of such etching, the SiO₂ layer 57constituting the second hard mask 58 is also etched and is left like analmost cone shape.

Then, as shown in FIG. 18G, the SiO₂ layer 57 constituting the secondhard mask 58 is removed by the two-frequency reactive ion etching(two-frequency RIE) using a mixed gas consisting of C₄F₈, Ar, and O₂. Atthe time of such etching, for example, a power supply of 2000 W and27.13 MHz is connected to the upper electrode out of the parallel-platetype electrodes in the reaction chamber of the two-frequency RIEequipment and a power supply of 200 W and 800 kHz is connected to thelower electrode thereof. Also, a distance between the lower electrodeand the upper electrode is set to 20 mm. The temperature of the upperelectrode is set to 30° C., and the temperature of the lower electrodeon which the silicon substrate 1 is loaded is set to 0° C. Also, thetemperature of the inner side wall of the reaction chamber is set to 50°C. Also, as the etching gas, C₄F₈, Ar, and O₂ are introduced into thereaction chamber at a flow rate of 20 sccm, 500 sccm, and 8 sccmrespectively. Also, a gas pressure in the reaction chamber is set to 25to 40 mTorr.

In this case, if the sacrifice oxide layer 63 is left on the insulatingadhesive layer 62, such sacrifice oxide layer 63 as well as the SiO₂layer 57 is removed.

Then, the TiN layer 56 of the second hard mask 58 is removed by the wetetching using a mixed chemical consisting of hydrogen peroxide andammonia.

Then, in order to recover the damage of the ferroelectric layer 15caused by the etching that is executed to form the capacitors Q, therecovery annealing of the capacitors Q is executed. The recoveryannealing in this case is executed at the substrate temperature of 650°C. for 60 min in the atmosphere containing the oxygen, for example.

Then, like the second embodiment, steps goes to the steps of forming theinsulating capacitor protection layer 18, the second interlayerinsulating layer 19, the fourth conductive plug 21, etc., but theirdetails will be omitted herein.

In the above embodiments, the island-like oxygen barrier metal layer 11b and the overlying first hard mask 60 a are covered with thealumina-oxidation preventing insulating layer 62. Then, the first hardmask 60 a is removed at the same time when the alumina-oxidationpreventing insulating layer 62 is planarized by the CMP method.Therefore, like the eighth embodiment, there is no necessity toindependently provide the step of removing the first hard mask 60 a.

Also, the alumina layer has two times an oxidation preventing functionin contrast to the SiON layer. Thus, in order to prevent the oxidationof the second and third conductive plugs 10 b, 10 c at the time ofoxygen annealing after the formation of the island-like oxygen barriermetal layer 11 b, a thickness of the alumina-oxidation preventinginsulating layer 62 may be thinned such as about 50 nm.

The selective etching ratio of the SiO₂ layer to the alumina layer isabout 40. Hence, an etching depth of the alumina-oxidation preventinginsulating layer 62 generated when the SiO₂ layer 57 of the second hardmask 58 is removed by the etching is about 18 to 25 nm. Also, an etchingdepth of the alumina-oxidation preventing insulating layer 62 generatedby the overetching after the patterning of the capacitors Q is about 12to 17 nm.

The thickness of the alumina-oxidation preventing insulating layer 62may be set to about 100 nm or more with regard to these etching amounts.Therefore, if the alumina-oxidation preventing insulating layer 62 isplanarized by the CMP method, the thickness of the oxygen barrier metallayer 11 b serving as the stopper can be reduced to about 200 nm. As aresult, if the distance between the island-like oxygen barrier metallayers 11 b is narrowed, an increase in the aspect ratio of the spacebetween the oxygen barrier metal layers 11 b can be prevented. Thus, thealumina-oxidation preventing insulating layer 62 formed in the space canbe perfectly buried.

Because no clearance is generated in the alumina-oxidation preventinginsulating layer 62 in such space, no recess is formed in the firstinterlayer insulating layer 8 under the space between the island-likeoxygen barrier metal layers 11 b. Thus, the oxidation of the first tothird conductive plugs 10 a to 10 c through the first interlayerinsulating layer 8 can be prevented.

Also, in order to prevent the oxidation of the second and thirdconductive plugs 10 b, 10 c caused by the crystallization annealing ofthe ferroelectric layer 15 and the recovery annealing after theformation of the capacitors Q, the thickness of the Ir layerconstituting the oxygen barrier metal layer 11 b together with thethickness of the Ir layer 14 w constituting the lower electrode 14 a ofthe capacitor Q may be set to 300 nm or more. In addition, such layerthickness may be increased further more to meet with the oxidizingannealing temperature after the patterning of the oxygen barrier metallayer 11 b.

By the way, in the present embodiment, the thickness of the Ir layerconstituting the island-like oxygen barrier metal layer 11 b is set to200 nm with regard to the thickness of the Ir layer 14 w of the lowerelectrode 14 a. If the hard mask is formed as the single-layer structureof the TiN layer, there is no trouble to pattern such Ir layer havingthe thickness of 200 nm.

In this case, the above oxidation preventing insulating layer 62 has thealumina single-layer structure. But the double-layered structureconsisting of SiO₂ layer and the alumina layer or the double-layeredstructure consisting of the SiON layer and the alumina layer may beemployed.

Other Embodiment

In the above embodiments, doped silicon may be employed as the materialof the conductive plug.

Also, the ferroelectric material is employed as the dielectric layer ofthe capacitor, but the high-dielectric material may also be employed. Inaddition, the memory cell is explained in the above embodiments.Further, as explained in the first, second, and fifth embodiments, inthe peripheral circuit or the logic circuit formed on the semiconductorsubstrate, the step of forming the oxidation-preventing insulating layeron the first-layer conductive plug may be contained. In this case, inthe peripheral circuit or the logic circuit, the structure on theimpurity diffusion region may be formed as the structure that connectsthe conductive plug formed in the contact hole in the first interlayerinsulating layer 8 and the conductive plug formed in the contact hole inthe oxidation-preventing insulating layer 12 and the second interlayerinsulating layer 19, like the structure on the first n-type impuritydiffusion region 5 a. The impurity diffusion regions are thesource/drain regions of the MOS transistor, for example.

Also, as explained in the third, fourth, and seventh embodiments, in theperipheral circuit or the logic circuit, the structure on the impuritydiffusion regions constituting the MOS transistor may be formed as thestructure that connects sequentially the conductive plug formed in thecontact hole in the first interlayer insulating layer 8 and theconductive plug formed, the island-like oxygen-barrier metal layerformed on the first interlayer insulating layer, and the conductive plugformed in the second interlayer insulating layer.

In addition, ruthenium may be employed as the oxygen-barrier metal layerin place of iridium. Also, the oxygen-barrier metal layer may be formedof a ruthenium lower layer and a ruthenium oxide upper layer.

As described above, according to the present invention, the first andsecond conductive plugs are formed in the first insulating layer, thenthe oxygen-barrier metal layer is formed on the first conductive plugand the oxidation-preventing insulating layer is formed on the secondconductive plug, then the capacitors are formed on the first conductiveplug via the oxygen-barrier metal layer, then the second insulatinglayer for covering the capacitors is formed, and then the thirdconductive plug is formed on the second conductive plug. Therefore, thestructure for connecting the impurity diffusion region and the upperwiring is made on a via-to-via basis, and it is not needed to form theholes having the large aspect ratio at a time, and the filling of theholes can be facilitated. As a result, the up-to-date equipment is notrequired, and the development cost and the step cost can be reduced.Also, the abnormal oxidation of the first conductive plug can beprevented by the oxygen-barrier metal layer, and also the abnormaloxidation of the second conductive plug can be prevented by theoxidation-preventing insulating layer.

In addition, since the oxygen-barrier metal layer and the insulatingadhesion layer are planarized simultaneously by the polishing, thecapacitor lower electrode formed on the oxygen-barrier metal layer canbe formed flat. Thus, generation of the degradation of the dielectriclayer formed on the lower electrode can be avoided, and also formationof the capacitors with good characteristics can be formed.

Further, by adopting the oxygen-barrier metal layer formed as themulti-layered structure and the upper layer is formed of the materialthat can be relatively easily polished, e.g., iridium oxide, theunderlying layer of the capacitors can be formed flatter by polishingthe insulating adhesion layer and the oxygen-barrier metal layer. Thus,the characteristics of the capacitors can be improved.

Furthermore, according to the present invention, the oxygen-barriermetal layer instead of the oxidation-preventing insulating layer isformed like the island on the second conductive plug. Therefore, notonly the same advantages as the oxidation-preventing insulating layercan be obtained but also the step of forming the oxidation-preventinginsulating layer can be omitted.

In this case, by adopting the oxygen-barrier metal layer formed on thefirst conductive plug immediately under the capacitor as the lowerelectrode, the step of patterning the lower electrode can be reduced.

In the condition of which the conductive adhesion layer is formedbetween the conductive layer constituting the capacitor lower electrodeand the oxygen-barrier metal layer, the peeling-off of the capacitorlower electrode can be prevented without fail.

By adopting the conductive adhesion layer formed between theoxygen-barrier metal layer and the first insulating layer, the adherencebetween the oxygen-barrier metal layer and the first insulating layercan be improved. Therefore, the oxygen can be prevented without failfrom being supplied from the clearance between the oxygen-barrier metallayer and the first insulating layer to the conductive plug, and thusthe oxidation of the conductive plug can be prevented.

In the case that the oxygen-barrier metal layer is patterned by usingthe hard masks, the insulating adhesion layer is formed on the hardmasks and the oxidation-preventing insulating layer after the patterningof the oxygen-barrier metal layer, and then the insulating adhesionlayer and the hard masks are polished continuously until theoxygen-barrier metal layer is exposed. Therefore, the independent stepof removing the hard masks can be omitted and thus throughput can beimproved.

1. A semiconductor device comprising: a first impurity diffusion regionand a second impurity diffusion region formed in a surface region of asemiconductor substrate; a first insulating layer formed over thesemiconductor substrate; a first hole and a second hole formed in thefirst insulating layer; a first conductive plug formed in the first holeand connected electrically to the first impurity diffusion region; asecond conductive plug formed in the second hole and connectedelectrically to the second impurity diffusion region; an oxygen-barriermetal layer formed in a shape of an island on the first conductive plugand its peripheral area and on the first insulating layer, said oxygenbarrier metal layer having a side surface; an oxidation preventing layerformed on the first insulating layer and side surface of theoxygen-barrier metal layer and made of material that prevents oxidationof the second conductive plug, an upper surface of the oxidationpreventing layer being planarized around the oxygen-barrier metal layer;a capacitor having a lower electrode formed on the oxygen-barrier metallayer, a dielectric layer formed on the lower electrode, and an upperelectrode formed on the dielectric layer; a second insulating layercovering the capacitor and the oxidation preventing layer; a third holeformed in the second insulating layer over the second conductive plug;and a third conductive plug formed in the third hole and connectedelectrically to the second conductive plug; wherein an island-likeconductive layer formed of same conductive material as theoxygen-barrier metal layer is formed on the second conductive layer, andthe third conductive plug is connected to the second conductive plug viathe island-like conductive layer.
 2. A semiconductor device according toclaim 1, wherein an oxidation preventing insulating layer is formed onside surfaces of the island-like conductive layer, side surfaces of theoxygen-barrier metal layer, and an upper surface of the first insulatinglayer.
 3. A semiconductor device according to claim 1, wherein theoxygen-barrier metal layer constitutes a lower layer portion of thelower electrode of the capacitor.
 4. A semiconductor device according toclaim 1, wherein the oxygen-barrier metal layer has a substantially samesize as the lower electrode of the capacitor.
 5. A semiconductor deviceaccording to claim 1, wherein the oxygen-barrier metal layer consists ofconductive layers, and an uppermost layer of the conductive layers isformed of conductive material that is polished more easily than thelowermost layer of the conductive layers.
 6. A semiconductor deviceaccording to claim 1, wherein a conductive adhesion layer is formedbetween the oxygen-barrier metal layer and the lower electrode.
 7. Asemiconductor device according to claim 6, wherein an upper surface ofthe conductive adhesion layer has a same shape as a lower surface of thelower electrode.
 8. A semiconductor device according to claim 6, whereinthe oxygen-barrier metal layer is formed of same material as theconductive adhesion layer, and the conductive adhesion layer is formedat a position higher than the oxidation preventing insulating layer. 9.A semiconductor device according to claim 6, wherein the conductiveadhesion layer is formed of iridium.
 10. A semiconductor deviceaccording to claim 1, wherein a conductive adhesion layer is formedunder the oxygen-barrier metal layer and on the first insulating layerover the first conductive plug and a peripheral area of the firstconductive plug.
 11. A semiconductor device according to claim 10,wherein the conductive adhesion layer is formed by either a single-layerstructure made of titanium or titanium nitride or a double-layeredstructure constructed by forming titanium and titanium nitridesequentially.
 12. A manufacturing method of a semiconductor devicecomprising the steps of: forming a first impurity diffusion region and asecond impurity diffusion region on a surface region of a semiconductorsubstrate; forming a first insulating layer over the semiconductorsubstrate; forming a first hole and a second hole in the firstinsulating layer; forming a first conductive plug, which is connectedelectrically to the first impurity diffusion region, in the first holeand simultaneously forming a second conductive plug, which is connectedelectrically to the second impurity diffusion region, in the secondhole; forming an oxygen-barrier metal layer on the first conductive plugand on the second conductive plug and over the first insulating layer;patterning the oxygen-barrier metal layer to leave the oxygen-barriermetal layer like an island on the first conductive plug; forming anoxidation preventing insulating layer on the second conductive plug andover the first insulating layer; exposing an upper surface of theoxygen-barrier metal layer like the island by polishing the oxidationpreventing insulating layer; forming a first conductive layer on theoxygen-barrier metal layer like the island and over the oxidationpreventing insulating layer; forming a dielectric layer on the firstconductive layer; forming a second conductive layer on the dielectriclayer; forming a capacitor on the oxygen-barrier metal layer over thefirst conductive plug by patterning the second conductive layer, thedielectric layer, and the first conductive layer; forming a secondinsulating layer over the capacitor, and the oxidation preventinginsulating layer; forming a third hole over the second conductive plugby patterning the second insulating layer; and forming a thirdconductive plug, which is connected electrically to the secondconductive plug, in the third hole.
 13. A manufacturing method of asemiconductor device according to claim 12, further comprising the stepsof: forming an insulating adhesion layer over the oxidation preventinginsulating layer, planarizing the insulating adhesion layer and theoxidation preventing insulating layer at the same time; and forming thethird hole also in the insulating adhesion layer.
 14. A manufacturingmethod of a semiconductor device according to claim 12, furthercomprising the steps of: patterning the oxygen-barrier metal layer toleave the oxygen-barrier metal layer as an oxidation preventingconductive layer like an island on the second conductive plug andperipheral area of the second conductive plug; forming the third hole onthe oxidation preventing conductive layer made of the oxygen-barriermetal layer; and forming the third conductive plug in the third hole tobe connected to the second conductive plug electrically via theoxidation preventing conductive layer.
 15. A manufacturing method of asemiconductor device according to claim 12, wherein the oxygen-barriermetal layer is patterned as a part of the lower electrode of thecapacitor.
 16. A manufacturing method of a semiconductor deviceaccording to claim 12, wherein the oxygen-barrier metal layer ispatterned to have a substantially same size as the lower electrode ofthe capacitor.
 17. A manufacturing method of a semiconductor deviceaccording to claim 12, wherein the oxygen-barrier metal layer consistsof a lower layer and an upper layer, both made of different material,and the upper layer is made of a second material that is polished moreeasily than a first material constituting the lower layer.
 18. Amanufacturing method of a semiconductor device according to claim 12,further comprising the steps of: forming a conductive adhesion layerbetween the oxygen-barrier metal layer like island and the firstconductive layer; and patterning the conductive adhesion layer togetherwith the first conductive layer into an island shape.
 19. Amanufacturing method of a semiconductor device according to claim 12,further comprising the steps of: forming a conductive adhesion layerbetween the oxygen-barrier metal layer and the first insulating layer;and patterning the conductive adhesion layer together with theoxygen-barrier metal layer into the island shape.
 20. A manufacturingmethod of a semiconductor device according to claim 12, furthercomprising the steps of: forming a hard mask on the oxygen-barrier metallayer and over the first conductive plug; and etching a part of theoxygen-barrier metal layer exposed from the hard mask to leave theoxygen-barrier metal layer like the island.
 21. A manufacturing methodof a semiconductor device according to claim 12, further comprising thesteps of: removing the hard mask to expose the upper surface of theoxygen-barrier metal layer like the island by polishing, after coveringthe hard mask with the oxidation preventing insulating layer.
 22. Amanufacturing method of a semiconductor device according to claim 21,wherein the hard mask is formed of same material as materialconstituting a part of the second conductive plug.
 23. A manufacturingmethod of a semiconductor device according to claim 21, wherein an upperportion of the hard mask consists of silicon oxidation.
 24. Amanufacturing method of a semiconductor device according to claim 21,wherein the oxidation preventing insulating layer consists of one of asingle layer of alumina and a plural layer having alumina.
 25. Asemiconductor device according to claim 1, wherein an upper surface ofthe first conductive plug is located lower than an upper surface of theoxidation preventing layer.